[PATCH] D148874: [RISCV][CodeGen] Support Zfinx codegen

[Shao-Ce SUN via Phabricator via llvm-commits]

sunshaoce marked 2 inline comments as done.
sunshaoce added a comment.

In D148874#4288305 <https://reviews.llvm.org/D148874#4288305>, @craig.topper wrote:

> Do we need any changes for GPRF32 in RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot?



- I tried to add a diff, but the test file didn't change at all.

  diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  index b41f7afc1aa5..8ea0b5d4bce4 100644
  --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  @@ -524,6 +524,9 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
       Opcode = RISCV::FSW;
       IsScalableVector = false;
  +  } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
  +    Opcode = RISCV::SW;
  +    IsScalableVector = false;
     } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
       Opcode = RISCV::FSD;
       IsScalableVector = false;
  @@ -608,6 +611,9 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
       Opcode = RISCV::FLW;
       IsScalableVector = false;
  +  } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
  +    Opcode = RISCV::LW;
  +    IsScalableVector = false;
     } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
       Opcode = RISCV::FLD;
       IsScalableVector = false;



- RISCV::GPRF32RegClass uses the same registers as RISCV::GPRRegClass in practice. In RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot, the corresponding load/store will be selected.

  if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
             RISCV::SW : RISCV::SD;
    IsScalableVector = false;
  }

- So is it possible that RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot don't need to be modified?


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  https://reviews.llvm.org/D148874/new/

https://reviews.llvm.org/D148874