[PATCH] D148874: [RISCV][CodeGen] Support Zfinx codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4214
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
       return FPConv;
----------------
Is FMV_W_X_RV64 correct for Zfinx?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8888
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
----------------
Is FMV_X_ANYEXTW_RV64 correct for Zfinx?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:15212
   case MVT::f32:
-    return Subtarget.hasStdExtF();
+    return Subtarget.hasStdExtFOrZfinx();
   case MVT::f64:
----------------
This is a vector related function. I don't think this change is tested in this patch


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:432
+
+// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them
+// zero weight.
----------------
Why are these CSR aliases copied?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D148874/new/

https://reviews.llvm.org/D148874