[PATCH] D149001: [InstSimplify] sdiv a (1 srem b) --> a
Nikita Popov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 23 00:52:19 PDT 2023
nikic requested changes to this revision.
nikic added a comment.
This revision now requires changes to proceed.
Thanks! This will still a miss other patterns that can only be zero or one. For example a mask with 1: https://alive2.llvm.org/ce/z/A_ffYe
You can handle these by calling computeKnownBits() and checking the number of leading zeros.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D149001/new/
https://reviews.llvm.org/D149001
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