[PATCH] D148834: [RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:815
+  switch (LMUL) {
+  default: break;
+  case LMUL_1: return true;
----------------
asb wrote:
> Would it be better to change this to case `LMUL_RESERVED: llvm_unreachable("reserved LMUL value")` so `-Wswitch` will pick up if the enumeration is expanded.
Can we use 

```
auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL);
return Fractional || LMul == 1;
```


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:854
 
+  // A slidedown/slideup with a VL of 1 whose destination is a IMPLICIT_DEF
+  // can use any VL/SEW combination which writes at least the first element.
----------------
"a IMPLICIT_DEF" -> "an IMPLICIT_DEF"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148834/new/

https://reviews.llvm.org/D148834