[PATCH] D148843: [X86 isel] Fix operand ordering in lowerShuffleAsUNPCKAndPermute

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

> Chaging the permute mask calculation based on whether V1 and V2 are swapped could be troublesome

I'm not sure I follow why you think this could be a problem?



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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:13341
   unsigned UnpckOp = MatchLo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
-  SDValue Unpck = DAG.getNode(UnpckOp, DL, VT, Ops);
+  SDValue Unpck = DAG.getNode(UnpckOp, DL, VT, {V1, V2});
   return DAG.getVectorShuffle(VT, DL, Unpck, DAG.getUNDEF(VT), PermuteMask);
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We're going to see regressions from this, because by forcing the V1/V2 unpack order we lose any chance of making use of a better shuffles by V2/V1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148843/new/

https://reviews.llvm.org/D148843