[PATCH] D148843: [X86 isel] Fix operand ordering in lowerShuffleAsUNPCKAndPermute

[Han Zhu via Phabricator via llvm-commits]

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This fixes issue 62242 <https://github.com/llvm/llvm-project/issues/62242>

While the purpose of this code block is to check that the mask is interleaving
elements from V1 and V2:

  SDValue &Op = Ops[Elt & 1];
  if (M < NumElts && (Op.isUndef() || Op == V1))
    Op = V1;
  else if (NumElts <= M && (Op.isUndef() || Op == V2)) {
    Op = V2;
    NormM -= NumElts;
  } else
    return SDValue();

It can potentially swap the order of V1 and V2 in Ops and therefore also in the
unpck instruction generated below. But the permute mask is calculated assuming
the first operand being V1 and second V2, therefore causing a mis-compile.

Chaging the permute mask calculation based on whether V1 and V2 are swapped
could be troublesome. So I have opted to fix the order of V1 followed by V2 in
Ops. This also makes the output more consistent with the input ordering.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148843

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr62242.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll