[PATCH] D148834: [RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns

[Philip Reames via Phabricator via llvm-commits]

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Noticed this while looking at some SLP output.  If we have an extractelement, we're probably using a slidedown into an destination with no contents.  Given this, we can allow the slideup to use a larger VL and clobber tail elements of the destination vector.  Doing this allows us to avoid vsetvli toggles in many fixed length vector examples.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148834

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
  llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

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