[PATCH] D148733: [RISCV] Let assembler accept vector memory operands that have an explicit 0 offset.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG09b0f89c33f1: [RISCV] Let assembler accept vector memory operands that have an explicit 0… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148733/new/

https://reviews.llvm.org/D148733

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/zvlsseg.s

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