[PATCH] D148733: [RISCV] Let assembler accept vector memory operands that have an explicit 0 offset.

[Craig Topper via Phabricator via llvm-commits]

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Binutils allows vector instructions with memory operands that
have an explicit 0 offset like 'vle8.v v0, 0(a0)'.

We already have support for this in the parser because the same
thing is allowed for atomics.

This patch changes the AsmOperand and AsmString for the vector
memory instructions to allow this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148733

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/zvlsseg.s

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