[llvm] 05d04a0 - [AMDGPU] NFC. Refactor GISel for cmp intrinsics
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 19 08:34:02 PDT 2023
Author: Joe Nash
Date: 2023-04-19T11:33:47-04:00
New Revision: 05d04a0180c74b119db96b59c4230ad6f861e553
URL: https://github.com/llvm/llvm-project/commit/05d04a0180c74b119db96b59c4230ad6f861e553
DIFF: https://github.com/llvm/llvm-project/commit/05d04a0180c74b119db96b59c4230ad6f861e553.diff
LOG: [AMDGPU] NFC. Refactor GISel for cmp intrinsics
Combine the logic for fcmp and icmp intrinsics and use operand presence
instead.
Reviewed By: kosarev, foad
Differential Revision: https://reviews.llvm.org/D148716
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index df1fa2602e17f..67057fd0e5dc5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1291,27 +1291,26 @@ bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const {
if (Opcode == -1)
return false;
- MachineInstr *SelectedMI;
- if (CmpInst::isFPPredicate(Pred)) {
- MachineOperand &LHS = I.getOperand(2);
- MachineOperand &RHS = I.getOperand(3);
- auto [Src0, Src0Mods] = selectVOP3ModsImpl(LHS);
- auto [Src1, Src1Mods] = selectVOP3ModsImpl(RHS);
- Register Src0Reg =
- copyToVGPRIfSrcFolded(Src0, Src0Mods, LHS, &I, /*ForceVGPR*/ true);
- Register Src1Reg =
- copyToVGPRIfSrcFolded(Src1, Src1Mods, RHS, &I, /*ForceVGPR*/ true);
- SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst)
- .addImm(Src0Mods)
- .addReg(Src0Reg)
- .addImm(Src1Mods)
- .addReg(Src1Reg)
- .addImm(0); // clamp
- } else {
- SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst)
- .add(I.getOperand(2))
- .add(I.getOperand(3));
- }
+ MachineInstrBuilder SelectedMI;
+ MachineOperand &LHS = I.getOperand(2);
+ MachineOperand &RHS = I.getOperand(3);
+ auto [Src0, Src0Mods] = selectVOP3ModsImpl(LHS);
+ auto [Src1, Src1Mods] = selectVOP3ModsImpl(RHS);
+ Register Src0Reg =
+ copyToVGPRIfSrcFolded(Src0, Src0Mods, LHS, &I, /*ForceVGPR*/ true);
+ Register Src1Reg =
+ copyToVGPRIfSrcFolded(Src1, Src1Mods, RHS, &I, /*ForceVGPR*/ true);
+ SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst);
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers))
+ SelectedMI.addImm(Src0Mods);
+ SelectedMI.addReg(Src0Reg);
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1_modifiers))
+ SelectedMI.addImm(Src1Mods);
+ SelectedMI.addReg(Src1Reg);
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::clamp))
+ SelectedMI.addImm(0); // clamp
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel))
+ SelectedMI.addImm(0); // op_sel
RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI);
if (!constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI))
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