[PATCH] D147533: [AArch64][CodeGen][SME] Allow vectors large than hardware support to use SVE's load zero/sign-extend for fixed vectors

[Dinar Temirbulatov via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3e76d012d174: [AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's load… (authored by dtemirbulatov).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147533/new/

https://reviews.llvm.org/D147533

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll

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