[llvm] d9ed0de - [AMDGPU] Remove unused check lines from GlobalISel MIR tests
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 19 07:04:57 PDT 2023
Author: Jay Foad
Date: 2023-04-19T15:03:32+01:00
New Revision: d9ed0dee0c0e342204bb8ad0ff22a50d071c9443
URL: https://github.com/llvm/llvm-project/commit/d9ed0dee0c0e342204bb8ad0ff22a50d071c9443
DIFF: https://github.com/llvm/llvm-project/commit/d9ed0dee0c0e342204bb8ad0ff22a50d071c9443.diff
LOG: [AMDGPU] Remove unused check lines from GlobalISel MIR tests
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
index 8e03a2af71068..e6b108a558538 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
@@ -7,8 +7,6 @@ body: |
bb.0:
liveins: $sgpr0
- ; CHECK: $vgpr0 = COPY %3
- ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
; GCN-LABEL: name: rcp_sqrt_test
; GCN: liveins: $sgpr0
; GCN-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
index d40aa14d73a3b..6117ea7027416 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
@@ -18,21 +18,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX6-LABEL: name: ashr_v2s16_ss
- ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX6: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX7-LABEL: name: ashr_v2s16_ss
- ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX7: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX8-LABEL: name: ashr_v2s16_ss
- ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX8: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
; GFX9-LABEL: name: ashr_v2s16_ss
; GFX9: liveins: $sgpr0, $sgpr1
; GFX9-NEXT: {{ $}}
@@ -61,21 +46,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; GFX6-LABEL: name: ashr_v2s16_sv
- ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX7-LABEL: name: ashr_v2s16_sv
- ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX8-LABEL: name: ashr_v2s16_sv
- ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
; GFX9-LABEL: name: ashr_v2s16_sv
; GFX9: liveins: $sgpr0, $vgpr0
; GFX9-NEXT: {{ $}}
@@ -104,21 +74,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; GFX6-LABEL: name: ashr_v2s16_vs
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX7-LABEL: name: ashr_v2s16_vs
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX8-LABEL: name: ashr_v2s16_vs
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
; GFX9-LABEL: name: ashr_v2s16_vs
; GFX9: liveins: $sgpr0, $vgpr0
; GFX9-NEXT: {{ $}}
@@ -147,21 +102,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; GFX6-LABEL: name: ashr_v2s16_vv
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX6: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX7-LABEL: name: ashr_v2s16_vv
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX7: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
- ; GFX8-LABEL: name: ashr_v2s16_vv
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX8: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
; GFX9-LABEL: name: ashr_v2s16_vv
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
index e5ba07bbdad8d..0879258b8ee84 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
@@ -14,12 +14,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fabs_s32_ss
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
; SI-LABEL: name: fabs_s32_ss
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -62,12 +56,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fabs_s32_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
; SI-LABEL: name: fabs_s32_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -110,11 +98,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fabs_s32_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
- ; GCN: $vgpr0 = COPY [[FABS]](s32)
; SI-LABEL: name: fabs_s32_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -153,12 +136,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fabs_v2s16_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
; SI-LABEL: name: fabs_v2s16_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -201,12 +178,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fabs_s16_ss
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
; SI-LABEL: name: fabs_s16_ss
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -251,12 +222,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fabs_s16_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
- ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
; SI-LABEL: name: fabs_s16_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -302,13 +267,6 @@ body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fabs_s16_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
- ; GCN: $vgpr0 = COPY [[COPY1]](s32)
; SI-LABEL: name: fabs_s16_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -357,12 +315,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fabs_v2s16_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
- ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
; SI-LABEL: name: fabs_v2s16_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -405,11 +357,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fabs_v2s16_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
- ; GCN: $vgpr0 = COPY [[FABS]](<2 x s16>)
; SI-LABEL: name: fabs_v2s16_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -448,15 +395,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fabs_s64_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fabs_s64_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -511,15 +449,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GCN-LABEL: name: fabs_s64_vv
- ; GCN: liveins: $vgpr0_vgpr1
- ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY1]], implicit $exec
- ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fabs_s64_vv
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
@@ -574,11 +503,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fabs_s64_vs
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; GCN: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
- ; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
; SI-LABEL: name: fabs_s64_vs
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -618,15 +542,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GCN-LABEL: name: fabs_s64_vv_no_src_constraint
- ; GCN: liveins: $vgpr0_vgpr1
- ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fabs_s64_vv_no_src_constraint
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
@@ -681,15 +596,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fabs_s64_ss_no_src_constraint
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
- ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fabs_s64_ss_no_src_constraint
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
index b9251f2efe820..c2d4268699ef9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
@@ -82,14 +82,6 @@ body: |
bb.0:
liveins: $vgpr0
- ; SI-LABEL: name: ffloor_fneg_s16_vv
- ; SI: liveins: $vgpr0
- ; SI: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; SI: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
- ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
- ; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16)
- ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: ffloor_fneg_s16_vv
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
index acf25f1060d2f..03ebac714fd1e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
@@ -14,12 +14,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_s32_ss
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
; SI-LABEL: name: fneg_s32_ss
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -62,12 +56,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fneg_s32_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
; SI-LABEL: name: fneg_s32_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -110,11 +98,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_s32_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]]
- ; GCN: $vgpr0 = COPY [[FNEG]](s32)
; SI-LABEL: name: fneg_s32_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -153,12 +136,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_s16_ss
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
- ; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
; SI-LABEL: name: fneg_s16_ss
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -203,12 +180,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fneg_s16_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
; SI-LABEL: name: fneg_s16_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -254,13 +225,6 @@ body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_s16_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]]
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16)
- ; GCN: $vgpr0 = COPY [[COPY1]](s32)
; SI-LABEL: name: fneg_s16_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -309,12 +273,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_v2s16_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
- ; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
; SI-LABEL: name: fneg_v2s16_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -357,12 +315,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fneg_v2s16_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
; SI-LABEL: name: fneg_v2s16_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -405,11 +357,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_v2s16_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]]
- ; GCN: $vgpr0 = COPY [[FNEG]](<2 x s16>)
; SI-LABEL: name: fneg_v2s16_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -448,15 +395,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_s64_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fneg_s64_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -511,15 +449,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GCN-LABEL: name: fneg_s64_vv
- ; GCN: liveins: $vgpr0_vgpr1
- ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY1]], implicit $exec
- ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_XOR_B32_e32_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fneg_s64_vv
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
@@ -574,11 +503,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_s64_vs
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; GCN: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]]
- ; GCN: S_ENDPGM 0, implicit [[FNEG]](s64)
; SI-LABEL: name: fneg_s64_vs
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -618,12 +542,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_fabs_s32_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: S_ENDPGM 0, implicit [[S_OR_B32_]]
; SI-LABEL: name: fneg_fabs_s32_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -667,12 +585,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fneg_fabs_s32_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: S_ENDPGM 0, implicit [[V_XOR_B32_e32_]]
; SI-LABEL: name: fneg_fabs_s32_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -716,13 +628,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_fabs_s32_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147483648
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(s32) = V_XOR_B32_e32 [[S_MOV_B32_]](s16), [[FABS]](s32), implicit $exec
- ; GCN: S_ENDPGM 0, implicit [[V_XOR_B32_e32_]](s32)
; SI-LABEL: name: fneg_fabs_s32_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -770,12 +675,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_fabs_s16_ss
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
- ; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_OR_B32_]]
; SI-LABEL: name: fneg_fabs_s16_ss
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -821,13 +720,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fneg_fabs_s16_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
- ; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e32_]]
- ; GCN: $vgpr0 = COPY [[COPY1]]
; SI-LABEL: name: fneg_fabs_s16_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -878,14 +770,6 @@ body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_fabs_s16_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GCN: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]]
- ; GCN: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]]
- ; GCN: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16)
- ; GCN: $vgpr0 = COPY [[COPY1]](s32)
; SI-LABEL: name: fneg_fabs_s16_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -939,12 +823,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_fabs_v2s16_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
- ; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: $sgpr0 = COPY [[S_OR_B32_]]
; SI-LABEL: name: fneg_fabs_v2s16_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -988,12 +866,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; GCN-LABEL: name: fneg_fabs_v2s16_vv
- ; GCN: liveins: $vgpr0
- ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
- ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]]
; SI-LABEL: name: fneg_fabs_v2s16_vv
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
@@ -1037,13 +909,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
- ; GCN-LABEL: name: fneg_fabs_v2s16_vs
- ; GCN: liveins: $sgpr0
- ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s16) = S_MOV_B32 2147516416
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_XOR_B32_e32 [[S_MOV_B32_]](s16), [[FABS]](<2 x s16>), implicit $exec
- ; GCN: $vgpr0 = COPY [[V_XOR_B32_e32_]](<2 x s16>)
; SI-LABEL: name: fneg_fabs_v2s16_vs
; SI: liveins: $sgpr0
; SI-NEXT: {{ $}}
@@ -1091,15 +956,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_fabs_s64_ss
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
- ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
- ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fneg_fabs_s64_ss
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
@@ -1155,15 +1011,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; GCN-LABEL: name: fneg_fabs_s64_vv
- ; GCN: liveins: $vgpr0_vgpr1
- ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY1]], implicit $exec
- ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e32_]], %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
; SI-LABEL: name: fneg_fabs_s64_vv
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
@@ -1219,16 +1066,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
- ; GCN-LABEL: name: fneg_fabs_s64_vs
- ; GCN: liveins: $sgpr0_sgpr1
- ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; GCN: [[FABS:%[0-9]+]]:vreg_64(s64) = G_FABS [[COPY]]
- ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub1(s64)
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32(s32) = S_MOV_B32 2147483648
- ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32(s16) = V_XOR_B32_e32 [[S_MOV_B32_]](s32), [[COPY1]](s32), implicit $exec
- ; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]].sub0(s64)
- ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64(s64) = REG_SEQUENCE [[COPY2]](s32), %subreg.sub0, [[V_XOR_B32_e32_]](s16), %subreg.sub1
- ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]](s64)
; SI-LABEL: name: fneg_fabs_s64_vs
; SI: liveins: $sgpr0_sgpr1
; SI-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
index a545afb77a0a8..7f37a26169609 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
@@ -18,21 +18,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX6-LABEL: name: lshr_v2s16_ss
- ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX6: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX7-LABEL: name: lshr_v2s16_ss
- ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX7: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX8-LABEL: name: lshr_v2s16_ss
- ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX8: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
; GFX9-LABEL: name: lshr_v2s16_ss
; GFX9: liveins: $sgpr0, $sgpr1
; GFX9-NEXT: {{ $}}
@@ -61,21 +46,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; GFX6-LABEL: name: lshr_v2s16_sv
- ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX7-LABEL: name: lshr_v2s16_sv
- ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX8-LABEL: name: lshr_v2s16_sv
- ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
; GFX9-LABEL: name: lshr_v2s16_sv
; GFX9: liveins: $sgpr0, $vgpr0
; GFX9-NEXT: {{ $}}
@@ -104,21 +74,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; GFX6-LABEL: name: lshr_v2s16_vs
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX7-LABEL: name: lshr_v2s16_vs
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX8-LABEL: name: lshr_v2s16_vs
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
; GFX9-LABEL: name: lshr_v2s16_vs
; GFX9: liveins: $sgpr0, $vgpr0
; GFX9-NEXT: {{ $}}
@@ -147,21 +102,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; GFX6-LABEL: name: lshr_v2s16_vv
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX6: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX7-LABEL: name: lshr_v2s16_vv
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX7: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
- ; GFX8-LABEL: name: lshr_v2s16_vv
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX8: [[LSHR:%[0-9]+]]:vgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>)
; GFX9-LABEL: name: lshr_v2s16_vv
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
index a11fcc3b5cd5a..6a4f821ab3b62 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
@@ -18,21 +18,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; GFX6-LABEL: name: shl_v2s16_ss
- ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX6: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX7-LABEL: name: shl_v2s16_ss
- ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX7: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX8-LABEL: name: shl_v2s16_ss
- ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
- ; GFX8: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
; GFX9-LABEL: name: shl_v2s16_ss
; GFX9: liveins: $sgpr0, $sgpr1
; GFX9-NEXT: {{ $}}
@@ -61,21 +46,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; GFX6-LABEL: name: shl_v2s16_sv
- ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX7-LABEL: name: shl_v2s16_sv
- ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX8-LABEL: name: shl_v2s16_sv
- ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
; GFX9-LABEL: name: shl_v2s16_sv
; GFX9: liveins: $sgpr0, $vgpr0
; GFX9-NEXT: {{ $}}
@@ -104,21 +74,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
- ; GFX6-LABEL: name: shl_v2s16_vs
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX6: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX7-LABEL: name: shl_v2s16_vs
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX7: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX8-LABEL: name: shl_v2s16_vs
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
- ; GFX8: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
; GFX9-LABEL: name: shl_v2s16_vs
; GFX9: liveins: $sgpr0, $vgpr0
; GFX9-NEXT: {{ $}}
@@ -147,21 +102,6 @@ regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; GFX6-LABEL: name: shl_v2s16_vv
- ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX6: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX7-LABEL: name: shl_v2s16_vv
- ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX7: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
- ; GFX8-LABEL: name: shl_v2s16_vv
- ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
- ; GFX8: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
- ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
; GFX9-LABEL: name: shl_v2s16_vv
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
index bb0830dffbdfe..26c3dad786be6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
@@ -13,20 +13,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
- ; WAVE64-LABEL: name: ubfx_s32_vii
- ; WAVE64: liveins: $vgpr0
- ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
- ; WAVE64: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
- ; WAVE64: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec
- ; WAVE64: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
- ; WAVE32-LABEL: name: ubfx_s32_vii
- ; WAVE32: liveins: $vgpr0
- ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
- ; WAVE32: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
- ; WAVE32: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec
- ; WAVE32: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
; CHECK-LABEL: name: ubfx_s32_vii
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
@@ -50,20 +36,6 @@ tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
- ; WAVE64-LABEL: name: ubfx_s32_vvv
- ; WAVE64: liveins: $vgpr0, $vgpr1, $vgpr2
- ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; WAVE64: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
- ; WAVE64: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
- ; WAVE32-LABEL: name: ubfx_s32_vvv
- ; WAVE32: liveins: $vgpr0, $vgpr1, $vgpr2
- ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
- ; WAVE32: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
- ; WAVE32: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
; CHECK-LABEL: name: ubfx_s32_vvv
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
index 67142e720219b..46ff290848f28 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
@@ -260,11 +260,6 @@ body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
- ; CHECK-LABEL: name: test_unmerge_s512_s1024
- ; CHECK: [[COPY:%[0-9]+]]:_(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
- ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](s1024)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[UV]](s512)
- ; CHECK: $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY [[UV1]](s512)
; GCN-LABEL: name: test_unmerge_values_s_s512_s_s1024
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GCN-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
index 71fb1b903b77c..92cde9de38cb7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
@@ -377,19 +377,6 @@ name: test_fadd_v3s16
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
- ; CHECK-LABEL: name: test_or_v3s16
- ; CHECK: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; CHECK: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
- ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0
- ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV2]](<3 x s16>), 0
- ; CHECK: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[INSERT]], [[INSERT1]]
- ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[OR]](<4 x s16>), 0
- ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
- ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>)
- ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; SI-LABEL: name: test_fadd_v3s16
; SI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; SI-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
index 9862028f8eeb1..296af2b2d4917 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
@@ -11,10 +11,6 @@ body: |
bb.0:
liveins: $vgpr0
- ; GFX89-LABEL: name: test_fexp2_s32
- ; GFX89: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX89: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[COPY]]
- ; GFX89: $vgpr0 = COPY [[FEXP2_]](s32)
; GFX6-LABEL: name: test_fexp2_s32
; GFX6: liveins: $vgpr0
; GFX6-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
index 5d34adb5affe4..8e999e400a666 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
@@ -425,19 +425,6 @@ name: test_fsub_v3s16
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
- ; CHECK-LABEL: name: test_or_v3s16
- ; CHECK: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr3_vgpr4_vgpr5
- ; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
- ; CHECK: [[UV2:%[0-9]+]]:_(<3 x s16>), [[UV3:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
- ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
- ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0
- ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV2]](<3 x s16>), 0
- ; CHECK: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[INSERT]], [[INSERT1]]
- ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[OR]](<4 x s16>), 0
- ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
- ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>)
- ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; SI-LABEL: name: test_fsub_v3s16
; SI: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
; SI-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
index b08632b81e114..0e6b692cbcfb8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
@@ -30,12 +30,6 @@ body: |
bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
- ; GVN-LABEL: name: test_sbfx_s64
- ; GVN: %copy:_(s64) = COPY $vgpr0_vgpr1
- ; GVN: %offset:_(s32) = COPY $vgpr2
- ; GVN: %width:_(s32) = COPY $vgpr3
- ; GVN: %sbfx:_(s64) = G_SBFX %copy, %offset(s32), %width
- ; GVN: $vgpr0_vgpr1 = COPY %sbfx(s64)
; GCN-LABEL: name: test_sbfx_s64
; GCN: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
; GCN-NEXT: {{ $}}
@@ -57,20 +51,6 @@ body: |
bb.0.entry:
liveins: $vgpr0, $vgpr1, $vgpr2
- ; GVN-LABEL: name: test_sbfx_s8
- ; GVN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GVN: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GVN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GVN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GVN: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GVN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GVN: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GVN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GVN: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GVN: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY5]], [[AND]](s32), [[AND1]]
- ; GVN: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SBFX]](s32)
- ; GVN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; GVN: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GCN-LABEL: name: test_sbfx_s8
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN-NEXT: {{ $}}
@@ -100,20 +80,6 @@ body: |
bb.0.entry:
liveins: $vgpr0, $vgpr1, $vgpr2
- ; GVN-LABEL: name: test_sbfx_s16
- ; GVN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GVN: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GVN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GVN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GVN: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GVN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GVN: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GVN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GVN: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GVN: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY5]], [[AND]](s32), [[AND1]]
- ; GVN: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SBFX]](s32)
- ; GVN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; GVN: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GCN-LABEL: name: test_sbfx_s16
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
index 077eb55220804..9436609ff6afd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
@@ -1160,7 +1160,6 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
- ; CHECK-LABEL: name: select_v4s16_vcc_sv
; FAST-LABEL: name: select_v4s16_vcc_sv
; FAST: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; FAST-NEXT: {{ $}}
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