[PATCH] D147533: [AArch64][CodeGen][SME] Allow vectors large than hardware support to use SVE's load zero/sign-extend for fixed vectors

[Dinar Temirbulatov via Phabricator via llvm-commits]

dtemirbulatov updated this revision to Diff 514943.
dtemirbulatov added a comment.

Rebasing after rGe6096871fdd4 <https://reviews.llvm.org/rGe6096871fdd49461687ff57c4882c76477d1d5cd> commit.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147533/new/

https://reviews.llvm.org/D147533

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll

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