[PATCH] D148519: [RISCV] Support vector strict rounding operations.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2583
+  }
+  SDValue BaseRes = DAG.getNode(BaseOpc, DL, VT, Src);
+  Chain = DAG.getMergeValues({Unorder.getValue(1), Fadd.getValue(1)}, DL);
----------------
fakepaper56 wrote:
> craig.topper wrote:
> > I'm not sure we can convert to the base opcode. I think we need to keep the chain through the expanded opcodes. We need to make sure rounding mode changes or reads of fflags that should logically happen after the rounding expansion can't move up. The fadd probably protects anything above from sinking down.
> Is the strict_nearbyint is the cause that we should not covert to base opcode? If some modification of FRM is after strict_nearbyint and we covert strict_nearbyint to nearbyint, it maybe let compiler move the modification of FRM before the nearbyint.
That is one case yes. I think we could also move a write of fflags before the integer conversion. The integer can cause an inexact exception. If the user was trying to clear that inexact exception, it would be a bug to move their fflag write earlier.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148519/new/

https://reviews.llvm.org/D148519