[PATCH] D148317: [RISCV] Remove SEW=8 case for floating point

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added a comment.

Thanks for working on this. I was going to add a similar patch today!



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Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:37
+                        !eq(mx, "MF4"): [16],
+                        !eq(mx, "MF8"): []);
+}
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Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed?

In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty?

I wonder whether we need a `MxListF` that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D148317/new/

https://reviews.llvm.org/D148317