[PATCH] D148234: [AArch64] Remove AND and FMOV between uaddlv an urshl

Fri Apr 14 00:29:07 PDT 2023

jaykang10 added a comment.

In D148234#4265961 <https://reviews.llvm.org/D148234#4265961>, @dmgreen wrote:

> I think the code generated by clang should be fine, for the most part. Intrinsics often produce a i32 (as opposed to i16) as it is a legal type, so the nodes become easier to legalize. That doesn't mean that in DAG we need to always represent it the same way. We could convert aarch64.neon.uaddlv to a AArch64ISD::UADDLV node, and have it produce different input/output types. I will try to put the shift patch I mentioned to you up into review, it has a problem with combining adds into ssra at the moment though.

Yep, Thanks!
Additionally, in the future, it could be good to use `f16` type, which is legal type, for the intrinsics with `f16` type. I guess it could be there was no `f16` type support in clang and llvm when the intrinsics were implemented

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https://reviews.llvm.org/D148234