[PATCH] D148234: [AArch64] Remove AND and FMOV between uaddlv an urshl

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I think the code generated by clang should be fine, for the most part. Intrinsics often produce a i32 (as opposed to i16) as it is a legal type, so the nodes become easier to legalize. That doesn't mean that in DAG we need to always represent it the same way. We could convert aarch64.neon.uaddlv to a AArch64ISD::UADDLV node, and have it produce different input/output types. I will try to put the shift patch I mentioned to you up into review, it has a problem with combining adds into ssra at the moment though.


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  https://reviews.llvm.org/D148234/new/

https://reviews.llvm.org/D148234