[PATCH] D147934: [RISCV] Support LLVM IR intrinsics for XSfvcp extension.

Thu Apr 13 23:41:47 PDT 2023

4vtomat added inline comments.

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Comment at: llvm/include/llvm/IR/IntrinsicsRISCVXsf.td:17
+                                [llvm_any_ty, llvm_anyint_ty]),
+                    !listconcat([IntrNoMem], !if(HasSE, [IntrHasSideEffects], []))>,
+          RISCVVIntrinsic {
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craig.topper wrote:
> 4vtomat wrote:
> > craig.topper wrote:
> > > craig.topper wrote:
> > > > Aren't we supposed to have ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>> for the immediate operands?
> > > That's what is in our downstream. And we use llvm_i32_ty for those operands.
> > You are right, we should have these properties, I've added and make them to XLenVT type instead of i32 type, so that we can skip scalar legalization in lowerVectorIntrinsicScalars.
> `ImmArg` automatically skips scalar legalization so that wouldn’t have been an issue.
> 
> We can use XLenVT.
Got it!

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td:503
+      defm : VPatVC_XV<"fv", "F" # vti.SEW # "V", vti,
+                       GetFTypeInfo<vti.SEW>.Scalar,
+                       GetFTypeInfo<vti.SEW>.ScalarRegClass, payload1>;
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craig.topper wrote:
> Isn't there already a Scalar and ScalarRegClass field in vti?
We want vector argument to be **integer** and scalar argument to be **float**, so that's why we need to convert only scalar to **float**.

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  https://reviews.llvm.org/D147934/new/

https://reviews.llvm.org/D147934