[PATCH] D147934: [RISCV] Support LLVM IR intrinsics for XSfvcp extension.

[Brandon Wu via Phabricator via llvm-commits]

4vtomat added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCVXsf.td:17
+                                [llvm_any_ty, llvm_anyint_ty]),
+                    !listconcat([IntrNoMem], !if(HasSE, [IntrHasSideEffects], []))>,
+          RISCVVIntrinsic {
----------------
craig.topper wrote:
> craig.topper wrote:
> > Aren't we supposed to have ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>> for the immediate operands?
> That's what is in our downstream. And we use llvm_i32_ty for those operands.
You are right, we should have these properties, I've added and make them to XLenVT type instead of i32 type, so that we can skip scalar legalization in lowerVectorIntrinsicScalars.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll:239
+
+declare void @llvm.riscv.sf.vc.x.se.e32m8.iXLen.i32.iXLen(iXLen, iXLen, iXLen, i32, iXLen)
+
----------------
craig.topper wrote:
> Why is there no test for the e64 version of this intrinsic?
I'm not sure what Nelson is concerning at that time, I guess it's because this test contains both 32 bits and 64 bits test, however e64 tests is not available in 32 bits target.


Repository:
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  https://reviews.llvm.org/D147934/new/

https://reviews.llvm.org/D147934