[PATCH] D148118: [AArch64][DAGCombiner]: combine <2xi64> mul add/sub.

[David Sherwood via Phabricator via llvm-commits]

david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.

LGTM! Can you fix the formatting issue before landing the patch please? Thanks!



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17827
+  if (N->getOperand(0)->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
+    if(N->getOpcode() == ISD::SUB)
+      // That invalidate the pattern for mls
----------------
nit: I think there is a formatting issue here and should be `if (N->getOpcode() == ISD::SUB)`


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https://reviews.llvm.org/D148118