[PATCH] D148118: [AArch64][DAGCombiner]: combine <2xi64> mul add/sub.

[hassnaaHamdi via Phabricator via llvm-commits]

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64-bit vector mul is not supported in NEON,
so we use the SVE's mul.
To improve the performance, we can go one step further,
and use SVE's add/sub, so that we can use SVE's mla/mls.
That works on these patterns:
// This works on the patterns of:
//   add v1, (mul v2, v3)
//   sub v1, (mul v2, v3)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148118

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

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