[PATCH] D147784: [RISCV] Remove is*Branch instruction flags from C_JR

[Job Noorman via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4acae5b2ade5: [RISCV] Remove is*Branch instruction flags from C_JR (authored by jobnoorman).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147784/new/

https://reviews.llvm.org/D147784

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -552,10 +552,8 @@
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
                       "c.jr", "$rs1">, Sched<[WriteJmpReg]> {
-  let isBranch = 1;
   let isBarrier = 1;
   let isTerminator = 1;
-  let isIndirectBranch = 1;
   let rs2 = 0;
 }
 


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