[llvm] 4acae5b - [RISCV] Remove is*Branch instruction flags from C_JR

[Job Noorman via llvm-commits]

Author: Job Noorman
Date: 2023-04-11T09:28:18+02:00
New Revision: 4acae5b2ade5f313e06ddfdf7ab70385ac79dd0e

URL: https://github.com/llvm/llvm-project/commit/4acae5b2ade5f313e06ddfdf7ab70385ac79dd0e
DIFF: https://github.com/llvm/llvm-project/commit/4acae5b2ade5f313e06ddfdf7ab70385ac79dd0e.diff

LOG: [RISCV] Remove is*Branch instruction flags from C_JR

As discussed in 1d1b3c49531b, instruction flags set in the *.td files
are under-approximations. For C_JR, isBranch and isConditionalBranch are
set even though it is used for for returns which are not considered
branches.

This patch proposes to remove those flags from C_JR. More detailed
analysis can be implemented in RISCVMCInstrAnalysis.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147784

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 91aaa43c3c9fe..a26d791a4cbdd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -552,10 +552,8 @@ def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
                       "c.jr", "$rs1">, Sched<[WriteJmpReg]> {
-  let isBranch = 1;
   let isBarrier = 1;
   let isTerminator = 1;
-  let isIndirectBranch = 1;
   let rs2 = 0;
 }