[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11427
+                            BaseLd->getMemOperand(), 0, VT.getStoreSize()));
+        DAG.makeEquivalentMemoryOrdering(BaseLd, WideLoad);
+        return WideLoad;
----------------
Do we need to call makeEquivalentMemoryOrdering on all the loads here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713