[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll:339-341
   %a = load <4 x i16>, ptr %x, align 1
   %b.gep = getelementptr i8, ptr %x, i64 %s
   %b = load <4 x i16>, ptr %b.gep, align 1
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luke wrote:
> @reames FYI, this mirrors the loads from SLP in x264 SAD which have an alignment of 1
For the purpose of this patch, please update the tests to have the required alignment and add a negative test for the unaligned case.  I think this case is generally useful, regardless of the outcome on the spec test.  

For x266 specifically, let's talk offline.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713