[PATCH] D147789: [CodeGenPrepare][RISCV] Reverse transform in CGP to use zero-compare branch
Yingwei Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 7 07:16:59 PDT 2023
dtcxzyw created this revision.
dtcxzyw added reviewers: SjoerdMeijer, nikic.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
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dtcxzyw requested review of this revision.
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This patch handles signed icmp cases of Add and Sub based on D101778 <https://reviews.llvm.org/D101778> if it guarantees no overflow after hoisting. For example:
https://alive2.llvm.org/ce/z/wbCO7s
define i32 @src(i32 %0) {
%x = icmp sge i32 %0, 0
br i1 %x, label %nonnegative, label %5
nonnegative: ; preds = %1
%2 = icmp slt i32 %0, 13
br i1 %2, label %5, label %3
3: ; preds = %nonnegative
%4 = add i32 %0, -13
ret i32 %4
5: ; preds = %nonnegative, %1
ret i32 0
}
define i32 @tgt(i32 %0) {
%x = icmp sge i32 %0, 0
br i1 %x, label %nonnegative, label %5
nonnegative: ; preds = %1
%2 = add i32 %0, -13
%3 = icmp slt i32 %2, 0
br i1 %3, label %5, label %4
4: ; preds = %nonnegative
ret i32 %2
5: ; preds = %nonnegative, %1
ret i32 0
}
This patch addresses performance regressions in RISC-V benchmarks reported by our CI <https://github.com/dtcxzyw/llvm-ci/issues/88>. I think this patch can protect against regressions from patch D147568 <https://reviews.llvm.org/D147568>.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D147789
Files:
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/test/CodeGen/RISCV/branch-on-zero.ll
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