[PATCH] D147096: AMDGPU: Created a sub-register class for the return address operand in the tail call return instruction
Changpeng Fang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 6 14:32:49 PDT 2023
cfang updated this revision to Diff 511530.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147096/new/
https://reviews.llvm.org/D147096
Files:
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
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