[PATCH] D147668: [RFC][X86 isel] Remove lane requirement from lowerShuffleAsUNPCKAndPermute

[Han Zhu via Phabricator via llvm-commits]

zhuhan0 updated this revision to Diff 511479.
zhuhan0 added a comment.

Improve the LO/HI matching logic. Essentially we want the masks to all be in the lower or higher-order bits but they can be in any lane.

Also normalized the masks (NormM = M - NumElts if Op == V2) so that the code is more concise.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147668/new/

https://reviews.llvm.org/D147668

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/oddshuffles.ll
  llvm/test/CodeGen/X86/pr61964.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll

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