[PATCH] D147721: [AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 6 09:29:52 PDT 2023


foad created this revision.
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This was causing two test failures when I applied D129208 <https://reviews.llvm.org/D129208> to enable
extra verification of LiveIntervals:

  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147721

Files:
  llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp


Index: llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -106,7 +106,7 @@
 
 // Optimize sequence
 //    %sel = V_CNDMASK_B32_e64 0, 1, %cc
-//    %cmp = V_CMP_NE_U32 1, %1
+//    %cmp = V_CMP_NE_U32 1, %sel
 //    $vcc = S_AND_B64 $exec, %cmp
 //    S_CBRANCH_VCC[N]Z
 // =>
@@ -294,7 +294,13 @@
 
       LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
       LIS->RemoveMachineInstrFromMaps(*Sel);
+      bool ShrinkSel = Sel->getOperand(0).readsReg();
       Sel->eraseFromParent();
+      if (ShrinkSel) {
+        // The result of the V_CNDMASK was a subreg def which counted as a read
+        // from the other parts of the reg. Shrink their live ranges.
+        LIS->shrinkToUses(SelLI);
+      }
     }
   }
 


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