[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11373
+        SDValue Ptr = Ld->getBasePtr();
+        if (Ptr.getOpcode() != ISD::ADD || Ptr.getOperand(0) != CurPtr)
+          return SDValue();
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This currently only works for strides that use an incremental pattern, e.g. `p, (+ p stride), (+ (+ p stride) stride), ...`
A strided load could also be represented with a pointer vector built by stepvector + multiply by stride


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11380
+          return SDValue();
+        if (Ld->getValueType(0) != BaseLdVT)
+          return SDValue();
----------------
Do we need to check the memory VT as well?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11391-11403
+    // A special case is if the stride is exactly the width of one of the loads,
+    // in which case it's contiguous and can be combined into a regular vle
+    // without changing the element size
+    if (auto *ConstStride = dyn_cast<ConstantSDNode>(Stride)) {
+      if (ConstStride->getZExtValue() == BaseLdVT.getFixedSizeInBits() / 8) {
+        SDValue WideLoad =
+            DAG.getLoad(VT, DL, BaseLd->getChain(), BasePtr,
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This bit could be target agnostic. I have a copy of a patch locally that puts this in DAGCombiner if that would be a better place


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll:57
 ; RV64-NEXT:    vse16.v v8, (a1)
 ; RV64-NEXT:    ret
   %a = load <4 x i16>, ptr %x
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This test case doesn't produce a `concat_vector v0, v1, v2`, it's some other pattern that doesn't get picked up by the combine. Should fix it at some point


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713