[PATCH] D147607: [RISCV] Add tests for loads and stores of illegal fixed length vectors

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 511158.
luke added a comment.

Add test case for loads and stores with align 1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147607/new/

https://reviews.llvm.org/D147607

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D147607.511158.patch
Type: text/x-patch
Size: 15820 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230405/44fff7c3/attachment.bin>