[PATCH] D147607: [RISCV] Add tests for loads and stores of illegal fixed length vectors

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll:23
+; RV64-NEXT:    ret
+  %x = load <5 x i8>, ptr %p
+  ret <5 x i8> %x
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This seems to be loading 8 bytes in the generated code. Should probably test with an explicit `align 1` on the load too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147607/new/

https://reviews.llvm.org/D147607