[PATCH] D147538: [RISCV] Add DAG combine to fold (add (setcc x, 0, setlt), -1) -> (sra x, xlen - 1)

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added a comment.
This revision now requires changes to proceed.

This is not correct for the add cases

A correct transform would be

fold (add (setcc x, 0, setlt), -1) -> (xor (sra x, xlen - 1), -1)
fold (add (setcc 0, x, setgt), -1) -> (xor (sra x, xlen - 1), -1)

But I'm not sure that's profitable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147538/new/

https://reviews.llvm.org/D147538