[PATCH] D147538: [RISCV] Add DAG combine to fold (add (setcc x, 0, setlt), -1) -> (sra x, xlen - 1)

[Liao Chunyu via Phabricator via llvm-commits]

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  The result of add/sub + setcc is 0 or 1 for all bits.
  The sra instruction get the same result.
  
  fold (add (setcc x, 0, setlt), -1) -> (sra x, xlen - 1)
  fold (add (setcc 0, x, setgt), -1) -> (sra x, xlen - 1)
  fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
  fold (sub 0, (setcc 0, x, setgt)) -> (sra x , xlen - 1)
  
  These testcases do not contain setgt, I can not find a testcase now.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147538

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/bittest.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
  llvm/test/CodeGen/RISCV/shift-amount-mod.ll
  llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

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