[PATCH] D146522: [RISCV] Model vlseg/vsseg in interleaved memory ops

[Luke Lau via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG971a4501f7f2: [RISCV] Model vlseg/vsseg in interleaved memory ops (authored by luke).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146522/new/

https://reviews.llvm.org/D146522

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll

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