[PATCH] D146522: [RISCV] Model vlseg/vsseg in interleaved memory ops

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM, though please add a FIXME with a short description of the illegal memory op cost bit.  i.e. explain why the if is needed in the code since it's non-obvious.

Your observation about the memory op cost for <6 x i8> is something we should follow up on.  That does sound surprising, and I affect it is negatively impacting e.g. SLP vectorization of short vectors.  Once you've done that, we can resimplify this code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146522/new/

https://reviews.llvm.org/D146522