[PATCH] D145301: Add more efficient vector bitcast for AArch64
Markus Everling via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 31 06:34:24 PDT 2023
Sp00ph added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19520-19523
+ ComparisonResult = DAG.getSetCC(
+ DL, VecVT, ComparisonResult,
+ DAG.getSplatBuildVector(VecVT, DL, DAG.getConstant(0, DL, MVT::i64)),
+ ISD::CondCode::SETNE);
----------------
Does this always produce the same result as the current implementation? If in general a trunc store would get lowered to something like this:
```
%trunc = trunc <N x i8> %vec to <N x i1>
store <N x i1> %trunc, ptr %dst
```
then I think the result would differ if e.g. the input was `<1 x i8> <i8 2>` (current implementation would store a 0, this PR would store a 1). This should be easily fixable though by doing `vec & splat(1) != splat(0)` instead of just `vec != splat(0)`.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D145301/new/
https://reviews.llvm.org/D145301
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