[PATCH] D145301: Add more efficient vector bitcast for AArch64

[Lawrence Benson via Phabricator via llvm-commits]

lawben updated this revision to Diff 510006.
lawben added a comment.

Changed large parts of where this conversion takes place.

It is now located in a) lowering BITCASTs and b) combining truncating stores. This is now more generic than my old 
appraoch. In most cases, there is no difference in generted code. In one or two places, we lose information about the original vector type, so the SETCC is truncated and we then 
perform the conversion on that truncated vector. So whiel this adds a vector extract instruction in some cases, it is more general overall and handles more cases.

Now also handles the cases described by @Sp00ph, i.e., we don't need a comparison for this to work, as we might add one ourselves.

This still needs handling of big endian systems. But I think this is in a stage that we can discuss the overall design: @dmgreem @Sp00ph @david-arm


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145301/new/

https://reviews.llvm.org/D145301

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vec-combine-compare-and-store.ll
  llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D145301.510006.patch
Type: text/x-patch
Size: 24593 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230331/2cffa3c3/attachment.bin>