[PATCH] D147322: [AArch64] Improve fshl cost modeling if 3rd arg is constant.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: dmgreen, ab, t.p.northover, aemerson.
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In that case, the cost for i32 and i64 should be 1 (a single EXTR
instruction). For v4i32 and v2i64 it should be 3 (USHR + SHL + ORR).

Integer types smaller than i32 will get legalized to i32 and share its
cost.

This recovers a SLP regression revealed by D140392 <https://reviews.llvm.org/D140392>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147322

Files:
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/AArch64/fshl.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/fshl.ll

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