[llvm] f231554 - [RISCV] Correct the EvenSrc/OddSrc computation in isInterleaveShuffle.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-30T15:52:24-07:00
New Revision: f2315545b2e4232afab636adb384a4a8e971b94e

URL: https://github.com/llvm/llvm-project/commit/f2315545b2e4232afab636adb384a4a8e971b94e
DIFF: https://github.com/llvm/llvm-project/commit/f2315545b2e4232afab636adb384a4a8e971b94e.diff

LOG: [RISCV] Correct the EvenSrc/OddSrc computation in isInterleaveShuffle.

StartIndexes[0] Tells exactly which source element is in element 0,
the even source. Nothing needs to be swapped.

Since we're dealing with power of 2 vector lengths, StartIndexes[0]
is almost always even so the condition here was never true. The
exception is when we're interleaving two 1 element vectors. In that
case StartIndexes[0] could be 1.

We recently hit a failure from this on a pulldown. I don't have
the reduced reproducer yet and my naive attempts at making an
interleave of 1 element vectors produces a slideup instead so don't
go through this path.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D147268

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 36ca6836bc48..d905806698ac 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3082,8 +3082,8 @@ static bool isInterleaveShuffle(ArrayRef<int> Mask, MVT VT, int &EvenSrc,
   if (!ShuffleVectorInst::isInterleaveMask(Mask, 2, Size * 2, StartIndexes))
     return false;
 
-  EvenSrc = StartIndexes[0] % 2 ? StartIndexes[1] : StartIndexes[0];
-  OddSrc = StartIndexes[0] % 2 ? StartIndexes[0] : StartIndexes[1];
+  EvenSrc = StartIndexes[0];
+  OddSrc = StartIndexes[1];
 
   // One source should be low half of first vector.
   if (EvenSrc != 0 && OddSrc != 0)

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
index a633dbe540fa..e25ffcc0922e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
@@ -665,17 +665,16 @@ define <8 x i32> @unary_interleave_v8i32(<8 x i32> %x) {
 }
 
 ; This interleaves the first 2 elements of a vector in opposite order. With
-; undefs for the remaining elements.
-; FIXME: We incorrectly swap the elements.
+; undefs for the remaining elements. We use to miscompile this.
 define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {
 ; V128-LABEL: unary_interleave_10uu_v4i8:
 ; V128:       # %bb.0:
 ; V128-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
 ; V128-NEXT:    vslidedown.vi v10, v8, 1
 ; V128-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
-; V128-NEXT:    vwaddu.vv v9, v8, v10
+; V128-NEXT:    vwaddu.vv v9, v10, v8
 ; V128-NEXT:    li a0, -1
-; V128-NEXT:    vwmaccu.vx v9, a0, v10
+; V128-NEXT:    vwmaccu.vx v9, a0, v8
 ; V128-NEXT:    vmv1r.v v8, v9
 ; V128-NEXT:    ret
 ;
@@ -683,9 +682,9 @@ define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {
 ; V512:       # %bb.0:
 ; V512-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; V512-NEXT:    vslidedown.vi v10, v8, 1
-; V512-NEXT:    vwaddu.vv v9, v8, v10
+; V512-NEXT:    vwaddu.vv v9, v10, v8
 ; V512-NEXT:    li a0, -1
-; V512-NEXT:    vwmaccu.vx v9, a0, v10
+; V512-NEXT:    vwmaccu.vx v9, a0, v8
 ; V512-NEXT:    vmv1r.v v8, v9
 ; V512-NEXT:    ret
   %a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>