[llvm] b975626 - [RISCV] Test case for D147268. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-30T15:51:23-07:00
New Revision: b9756260eea1c225e4c829127e55aeb974322ae8

URL: https://github.com/llvm/llvm-project/commit/b9756260eea1c225e4c829127e55aeb974322ae8
DIFF: https://github.com/llvm/llvm-project/commit/b9756260eea1c225e4c829127e55aeb974322ae8.diff

LOG: [RISCV] Test case for D147268. NFC

This test currently miscompiles.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
index 57312808ca9a2..a633dbe540fa8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
@@ -663,3 +663,32 @@ define <8 x i32> @unary_interleave_v8i32(<8 x i32> %x) {
   %a = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
   ret <8 x i32> %a
 }
+
+; This interleaves the first 2 elements of a vector in opposite order. With
+; undefs for the remaining elements.
+; FIXME: We incorrectly swap the elements.
+define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {
+; V128-LABEL: unary_interleave_10uu_v4i8:
+; V128:       # %bb.0:
+; V128-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
+; V128-NEXT:    vslidedown.vi v10, v8, 1
+; V128-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; V128-NEXT:    vwaddu.vv v9, v8, v10
+; V128-NEXT:    li a0, -1
+; V128-NEXT:    vwmaccu.vx v9, a0, v10
+; V128-NEXT:    vmv1r.v v8, v9
+; V128-NEXT:    ret
+;
+; V512-LABEL: unary_interleave_10uu_v4i8:
+; V512:       # %bb.0:
+; V512-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; V512-NEXT:    vslidedown.vi v10, v8, 1
+; V512-NEXT:    vwaddu.vv v9, v8, v10
+; V512-NEXT:    li a0, -1
+; V512-NEXT:    vwmaccu.vx v9, a0, v10
+; V512-NEXT:    vmv1r.v v8, v9
+; V512-NEXT:    ret
+  %a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
+  ret <4 x i8> %a
+}
+