[lld] dc90af5 - [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 30 15:28:56 PDT 2023
Author: Craig Topper
Date: 2023-03-30T15:28:44-07:00
New Revision: dc90af501f00bb0bbbfde2d90360f074922e3e81
URL: https://github.com/llvm/llvm-project/commit/dc90af501f00bb0bbbfde2d90360f074922e3e81
DIFF: https://github.com/llvm/llvm-project/commit/dc90af501f00bb0bbbfde2d90360f074922e3e81.diff
LOG: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1
Make F and Zfinx imply Zicsr.
Make G imply Zifencei.
This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.
See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D147179
Added:
Modified:
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
lld/test/ELF/lto/riscv-attributes.ll
lld/test/ELF/riscv-attributes.s
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/attribute-with-insts.s
llvm/test/MC/RISCV/attribute-with-option.s
llvm/test/MC/RISCV/attribute.s
llvm/test/MC/RISCV/invalid-attribute.s
llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
llvm/unittests/Support/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
index 9f4fca00a796e..9d95acc33dddc 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
@@ -21,10 +21,10 @@ unsigned long test_vlenb(void) {
return __riscv_vlenb();
}
//.
-// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
//.
-// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
//.
// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 6e1289df10c10..7f89344c1dc06 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -1,6 +1,6 @@
// RUN: %clang --target=riscv32-unknown-elf -march=rv32i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p0 -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p1 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv32-unknown-elf -march=rv32im -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
@@ -70,7 +70,7 @@
// RUN: %clang --target=riscv64-unknown-elf -march=rv64i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64i2p0 -### %s \
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64i2p1 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64im -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck %s
@@ -321,10 +321,10 @@
// RV32-IMINOR-MISS: error: invalid arch name 'rv32i2p',
// RV32-IMINOR-MISS: minor version number missing after 'p' for extension 'i'
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p1 -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p2 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR1 %s
-// RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
-// RV32-IMINOR1: version number 2.1 for extension 'i'
+// RV32-IMINOR1: error: invalid arch name 'rv32i2p2', unsupported
+// RV32-IMINOR1: version number 2.2 for extension 'i'
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixt2p -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 617be1d41c999..1bd10e96f15af 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -64,7 +64,7 @@
// RUN: -o - | FileCheck %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
// RUN: -o - | FileCheck %s
-// CHECK: __riscv_i 2000000{{$}}
+// CHECK: __riscv_i 2001000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -79,14 +79,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
-// CHECK-A-EXT: __riscv_a 2000000{{$}}
+// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
-// CHECK-F-EXT: __riscv_f 2000000{{$}}
+// CHECK-F-EXT: __riscv_f 2002000{{$}}
// CHECK-F-EXT: __riscv_fdiv 1
// CHECK-F-EXT: __riscv_flen 32
// CHECK-F-EXT: __riscv_fsqrt 1
@@ -95,7 +95,7 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
-// CHECK-D-EXT: __riscv_d 2000000{{$}}
+// CHECK-D-EXT: __riscv_d 2002000{{$}}
// CHECK-D-EXT: __riscv_fdiv 1
// CHECK-D-EXT: __riscv_flen 64
// CHECK-D-EXT: __riscv_fsqrt 1
@@ -214,7 +214,7 @@
// RUN: %clang -target riscv64-unknown-linux-gnu \
// RUN: -march=rv64izfhmin1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFHMIN-EXT %s
-// CHECK-ZFHMIN-EXT: __riscv_f 2000000{{$}}
+// CHECK-ZFHMIN-EXT: __riscv_f 2002000{{$}}
// CHECK-ZFHMIN-EXT: __riscv_zfhmin 1000000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -223,7 +223,7 @@
// RUN: %clang -target riscv64-unknown-linux-gnu \
// RUN: -march=rv64izfh1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
-// CHECK-ZFH-EXT: __riscv_f 2000000{{$}}
+// CHECK-ZFH-EXT: __riscv_f 2002000{{$}}
// CHECK-ZFH-EXT: __riscv_zfh 1000000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu \
diff --git a/lld/test/ELF/lto/riscv-attributes.ll b/lld/test/ELF/lto/riscv-attributes.ll
index eb99397bbda8c..802eac0bc5106 100644
--- a/lld/test/ELF/lto/riscv-attributes.ll
+++ b/lld/test/ELF/lto/riscv-attributes.ll
@@ -10,10 +10,10 @@
; CHECK: BuildAttributes {
; CHECK-NEXT: FormatVersion: 0x41
; CHECK-NEXT: Section 1 {
-; CHECK-NEXT: SectionLength: 61
+; CHECK-NEXT: SectionLength: 70
; CHECK-NEXT: Vendor: riscv
; CHECK-NEXT: Tag: Tag_File (0x1)
-; CHECK-NEXT: Size: 51
+; CHECK-NEXT: Size: 60
; CHECK-NEXT: FileAttributes {
; CHECK-NEXT: Attribute {
; CHECK-NEXT: Tag: 4
@@ -30,7 +30,7 @@
; CHECK-NEXT: Attribute {
; CHECK-NEXT: Tag: 5
; CHECK-NEXT: TagName: arch
-; CHECK-NEXT: Value: rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zbb1p0
+; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zbb1p0{{$}}
; CHECK-NEXT: }
; CHECK-NEXT: }
; CHECK-NEXT: }
@@ -38,10 +38,10 @@
;--- 1.s
.attribute 4, 16
-.attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
;--- 2.s
.attribute 4, 16
-.attribute 5, "rv32i2p0_m2p0_f2p0_d2p0_zbb1p0"
+.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0"
.attribute 6, 1
;--- a.ll
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index f95924be283d4..147312c70a1a0 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -66,10 +66,10 @@
# CHECK: BuildAttributes {
# CHECK-NEXT: FormatVersion: 0x41
# CHECK-NEXT: Section 1 {
-# CHECK-NEXT: SectionLength: 52
+# CHECK-NEXT: SectionLength: 61
# CHECK-NEXT: Vendor: riscv
# CHECK-NEXT: Tag: Tag_File (0x1)
-# CHECK-NEXT: Size: 42
+# CHECK-NEXT: Size: 51
# CHECK-NEXT: FileAttributes {
# CHECK-NEXT: Attribute {
# CHECK-NEXT: Tag: 4
@@ -80,7 +80,7 @@
# CHECK-NEXT: Attribute {
# CHECK-NEXT: Tag: 5
# CHECK-NEXT: TagName: arch
-# CHECK-NEXT: Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
+# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0{{$}}
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: }
@@ -89,10 +89,10 @@
# CHECK2: BuildAttributes {
# CHECK2-NEXT: FormatVersion: 0x41
# CHECK2-NEXT: Section 1 {
-# CHECK2-NEXT: SectionLength: 95
+# CHECK2-NEXT: SectionLength: 104
# CHECK2-NEXT: Vendor: riscv
# CHECK2-NEXT: Tag: Tag_File (0x1)
-# CHECK2-NEXT: Size: 85
+# CHECK2-NEXT: Size: 94
# CHECK2-NEXT: FileAttributes {
# CHECK2-NEXT: Attribute {
# CHECK2-NEXT: Tag: 4
@@ -119,7 +119,7 @@
# CHECK2-NEXT: Attribute {
# CHECK2-NEXT: Tag: 5
# CHECK2-NEXT: TagName: arch
-# CHECK2-NEXT: Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0
+# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
# CHECK2-NEXT: }
# CHECK2-NEXT: }
# CHECK2-NEXT: }
@@ -136,7 +136,7 @@
# CHECK3-NEXT: Attribute {
# CHECK3-NEXT: Tag: 5
# CHECK3-NEXT: TagName: arch
-# CHECK3-NEXT: Value: rv64i99p0
+# CHECK3-NEXT: Value: rv64i99p0{{$}}
# CHECK3-NEXT: }
# CHECK3-NEXT: }
# CHECK3-NEXT: }
@@ -144,18 +144,18 @@
#--- a.s
.attribute stack_align, 16
-.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
.attribute unaligned_access, 0
#--- b.s
.attribute stack_align, 16
-.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
.attribute priv_spec, 2
.attribute priv_spec_minor, 2
#--- c.s
.attribute stack_align, 16
-.attribute arch, "rv64i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+.attribute arch, "rv64i2p1_f2p2_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
.attribute unaligned_access, 1
.attribute priv_spec, 2
.attribute priv_spec_minor, 2
@@ -172,7 +172,7 @@
# UNRECOGNIZED_EXT1-NEXT: Attribute {
# UNRECOGNIZED_EXT1-NEXT: Tag: 5
# UNRECOGNIZED_EXT1-NEXT: TagName: arch
-# UNRECOGNIZED_EXT1-NEXT: Value: rv64i2p0_y2p0
+# UNRECOGNIZED_EXT1-NEXT: Value: rv64i2p1_y2p0{{$}}
# UNRECOGNIZED_EXT1-NEXT: }
# UNRECOGNIZED_EXT1-NEXT: }
# UNRECOGNIZED_EXT1-NEXT: }
@@ -185,7 +185,7 @@
.byte 1 # Tag_File
.long .Lend-.Lbegin
.byte 5 # Tag_RISCV_arch
-.asciz "rv64i2p0_y2p0"
+.asciz "rv64i2p1_y2p0"
.Lend:
#--- unrecognized_ext2.s
@@ -200,7 +200,7 @@
# UNRECOGNIZED_EXT2-NEXT: Attribute {
# UNRECOGNIZED_EXT2-NEXT: Tag: 5
# UNRECOGNIZED_EXT2-NEXT: TagName: arch
-# UNRECOGNIZED_EXT2-NEXT: Value: rv64i2p0_zmadeup1p0
+# UNRECOGNIZED_EXT2-NEXT: Value: rv64i2p1_zmadeup1p0{{$}}
# UNRECOGNIZED_EXT2-NEXT: }
# UNRECOGNIZED_EXT2-NEXT: }
# UNRECOGNIZED_EXT2-NEXT: }
@@ -213,7 +213,7 @@
.byte 1 # Tag_File
.long .Lend-.Lbegin
.byte 5 # Tag_RISCV_arch
-.asciz "rv64i2p0_zmadeup1p0"
+.asciz "rv64i2p1_zmadeup1p0"
.Lend:
#--- unrecognized_version.s
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 80ba9b5f97823..1c29ce2fbbfdd 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -153,6 +153,9 @@ Changes to the RISC-V Backend
* Assembler support for RV64E was added.
* Assembler support was added for the experimental Zicond (integer conditional
operations) extension.
+* I, F, D, and A extension versions have been update to the 20191214 spec versions.
+ New version I2.1, F2.2, D2.2, A2.1. This should not impact code generation.
+ Immpacts versions accepted in ``-march`` and reported in ELF attributes.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index ffb072677ec18..e890cca0d9062 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -39,13 +39,17 @@ struct RISCVSupportedExtension {
static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
+static const char *RISCVGImplications[] = {
+ "i", "m", "a", "f", "d", "zicsr", "zifencei"
+};
+
static const RISCVSupportedExtension SupportedExtensions[] = {
- {"i", RISCVExtensionVersion{2, 0}},
+ {"i", RISCVExtensionVersion{2, 1}},
{"e", RISCVExtensionVersion{2, 0}},
{"m", RISCVExtensionVersion{2, 0}},
- {"a", RISCVExtensionVersion{2, 0}},
- {"f", RISCVExtensionVersion{2, 0}},
- {"d", RISCVExtensionVersion{2, 0}},
+ {"a", RISCVExtensionVersion{2, 1}},
+ {"f", RISCVExtensionVersion{2, 2}},
+ {"d", RISCVExtensionVersion{2, 2}},
{"c", RISCVExtensionVersion{2, 0}},
{"h", RISCVExtensionVersion{1, 0}},
@@ -618,7 +622,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
case 'i':
break;
case 'g':
- // g = imafd
+ // g expands to extensions in RISCVGImplications.
if (Arch.size() > 5 && isDigit(Arch[5]))
return createStringError(errc::invalid_argument,
"version not supported for 'g'");
@@ -652,11 +656,12 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
// No matter which version is given to `g`, we always set imafd to default
// version since the we don't have clear version scheme for that on
// ISA spec.
- for (const auto *Ext : {"i", "m", "a", "f", "d"})
+ for (const auto *Ext : RISCVGImplications) {
if (auto Version = findDefaultVersion(Ext))
ISAInfo->addExtension(Ext, Version->Major, Version->Minor);
else
llvm_unreachable("Default extension version not found?");
+ }
} else {
// Baseline is `i` or `e`
if (auto E = getExtensionVersion(
@@ -897,10 +902,12 @@ Error RISCVISAInfo::checkDependency() {
return Error::success();
}
+static const char *ImpliedExtsF[] = {"zicsr"};
static const char *ImpliedExtsD[] = {"f"};
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
static const char *ImpliedExtsZfhmin[] = {"f"};
static const char *ImpliedExtsZfh[] = {"f"};
+static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZdinx[] = {"zfinx"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZhinx[] = {"zfinx"};
@@ -908,7 +915,7 @@ static const char *ImpliedExtsZve64d[] = {"zve64f"};
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
static const char *ImpliedExtsZve32f[] = {"zve32x"};
-static const char *ImpliedExtsZve32x[] = {"zvl32b"};
+static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
@@ -946,6 +953,7 @@ struct ImpliedExtsEntry {
// Note: The table needs to be sorted by name.
static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"d"}, {ImpliedExtsD}},
+ {{"f"}, {ImpliedExtsF}},
{{"v"}, {ImpliedExtsV}},
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
{{"zcb"}, {ImpliedExtsZcb}},
@@ -953,6 +961,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"zfa"}, {ImpliedExtsZfa}},
{{"zfh"}, {ImpliedExtsZfh}},
{{"zfhmin"}, {ImpliedExtsZfhmin}},
+ {{"zfinx"}, {ImpliedExtsZfinx}},
{{"zhinx"}, {ImpliedExtsZhinx}},
{{"zhinxmin"}, {ImpliedExtsZhinxmin}},
{{"zk"}, {ImpliedExtsZk}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index de36751662a68..3d3260d77d1b6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -10,6 +10,13 @@
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
+def FeatureStdExtZicsr
+ : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+ "'zicsr' (CSRs)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicsr),
+ "'Zicsr' (CSRs)">;
+
def FeatureStdExtM
: SubtargetFeature<"m", "HasStdExtM", "true",
"'M' (Integer Multiplication and Division)">;
@@ -36,7 +43,8 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
def FeatureStdExtF
: SubtargetFeature<"f", "HasStdExtF", "true",
- "'F' (Single-Precision Floating-Point)">;
+ "'F' (Single-Precision Floating-Point)",
+ [FeatureStdExtZicsr]>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
@@ -71,13 +79,6 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
-def FeatureStdExtZicsr
- : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
- "'zicsr' (CSRs)">;
-def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
- AssemblerPredicate<(all_of FeatureStdExtZicsr),
- "'Zicsr' (CSRs)">;
-
def FeatureStdExtZifencei
: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
"'zifencei' (fence.i)">;
@@ -110,7 +111,8 @@ def HasStdExtZfhOrZfhmin
def FeatureStdExtZfinx
: SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
- "'Zfinx' (Float in Integer)">;
+ "'Zfinx' (Float in Integer)",
+ [FeatureStdExtZicsr]>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -371,7 +373,7 @@ def FeatureStdExtZve32x
: SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
- [FeatureStdExtZvl32b]>;
+ [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
def FeatureStdExtZve32f
: SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index d37beaa76add8..ea978ee39b5e1 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -140,141 +140,141 @@
; CHECK: .attribute 4, 16
-; RV32M: .attribute 5, "rv32i2p0_m2p0"
-; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
-; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
-; RV32A: .attribute 5, "rv32i2p0_a2p0"
-; RV32F: .attribute 5, "rv32i2p0_f2p0"
-; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
-; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
-; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
-; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
-; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
-; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
-; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
-; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
-; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
-; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
-; RV32H: .attribute 5, "rv32i2p0_h1p0"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
-; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
-; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
-; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"
-; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"
-; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"
-; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"
-; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0"
-; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0"
-; RV32ZKR: .attribute 5, "rv32i2p0_zkr1p0"
-; RV32ZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
-; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
-; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0"
-; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
-; RV32COMBINEINTOZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
-; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
-; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
-; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
-; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
-; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
-; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
-; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
-; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
-; RV32XTHEADCMO: .attribute 5, "rv32i2p0_xtheadcmo1p0"
-; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p0_xtheadcondmov1p0"
-; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p0_f2p0_xtheadfmemidx1p0"
-; RV32XTHEADMAC: .attribute 5, "rv32i2p0_xtheadmac1p0"
-; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p0_xtheadmemidx1p0"
-; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p0_xtheadmempair1p0"
-; RV32XTHEADSYNC: .attribute 5, "rv32i2p0_xtheadsync1p0"
-; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0"
-; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
-; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
-; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
-; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
-; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
-; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1"
-; RV32ZVKB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
-; RV32ZVKG: .attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
-; RV32ZVKN: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNHA: .attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
-; RV32ZVKNHB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNED: .attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
-; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
-; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
-; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
-; RV32ZICOND: .attribute 5, "rv32i2p0_zicond1p0"
+; RV32M: .attribute 5, "rv32i2p1_m2p0"
+; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
+; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
+; RV32A: .attribute 5, "rv32i2p1_a2p1"
+; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
+; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
+; RV32C: .attribute 5, "rv32i2p1_c2p0"
+; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p1_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p1_zihintntl0p2"
+; RV32ZFHMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
+; RV32ZFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfh1p0"
+; RV32ZBA: .attribute 5, "rv32i2p1_zba1p0"
+; RV32ZBB: .attribute 5, "rv32i2p1_zbb1p0"
+; RV32ZBC: .attribute 5, "rv32i2p1_zbc1p0"
+; RV32ZBS: .attribute 5, "rv32i2p1_zbs1p0"
+; RV32V: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32H: .attribute 5, "rv32i2p1_h1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZBKB: .attribute 5, "rv32i2p1_zbkb1p0"
+; RV32ZBKC: .attribute 5, "rv32i2p1_zbkc1p0"
+; RV32ZBKX: .attribute 5, "rv32i2p1_zbkx1p0"
+; RV32ZKND: .attribute 5, "rv32i2p1_zknd1p0"
+; RV32ZKNE: .attribute 5, "rv32i2p1_zkne1p0"
+; RV32ZKNH: .attribute 5, "rv32i2p1_zknh1p0"
+; RV32ZKSED: .attribute 5, "rv32i2p1_zksed1p0"
+; RV32ZKSH: .attribute 5, "rv32i2p1_zksh1p0"
+; RV32ZKR: .attribute 5, "rv32i2p1_zkr1p0"
+; RV32ZKN: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV32ZKS: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV32ZKT: .attribute 5, "rv32i2p1_zkt1p0"
+; RV32ZK: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV32COMBINEINTOZK: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
+; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
+; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
+; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
+; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
+; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
+; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
+; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
+; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
+; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
+; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
+; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
+; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
+; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0"
+; RV32ZCD: .attribute 5, "rv32i2p1_zcd1p0"
+; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0"
+; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
+; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
+; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1"
+; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
-; RV64M: .attribute 5, "rv64i2p0_m2p0"
-; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
-; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
-; RV64A: .attribute 5, "rv64i2p0_a2p0"
-; RV64F: .attribute 5, "rv64i2p0_f2p0"
-; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
-; RV64C: .attribute 5, "rv64i2p0_c2p0"
-; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
-; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
-; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
-; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
-; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
-; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
-; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
-; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
-; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
-; RV64H: .attribute 5, "rv64i2p0_h1p0"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
-; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
-; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
-; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"
-; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"
-; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"
-; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"
-; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0"
-; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0"
-; RV64ZKR: .attribute 5, "rv64i2p0_zkr1p0"
-; RV64ZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
-; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
-; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0"
-; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
-; RV64COMBINEINTOZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
-; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
-; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
-; RV64ZICBOM: .attribute 5, "rv64i2p0_zicbom1p0"
-; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
-; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
-; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
-; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
-; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
-; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
-; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
-; RV64XTHEADBA: .attribute 5, "rv64i2p0_xtheadba1p0"
-; RV64XTHEADBB: .attribute 5, "rv64i2p0_xtheadbb1p0"
-; RV64XTHEADBS: .attribute 5, "rv64i2p0_xtheadbs1p0"
-; RV64XTHEADCMO: .attribute 5, "rv64i2p0_xtheadcmo1p0"
-; RV64XTHEADCONDMOV: .attribute 5, "rv64i2p0_xtheadcondmov1p0"
-; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p0_f2p0_xtheadfmemidx1p0"
-; RV64XTHEADMAC: .attribute 5, "rv64i2p0_xtheadmac1p0"
-; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p0_xtheadmemidx1p0"
-; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p0_xtheadmempair1p0"
-; RV64XTHEADSYNC: .attribute 5, "rv64i2p0_xtheadsync1p0"
-; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
-; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
-; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
-; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
-; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
-; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
-; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
-; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
-; RV64ZVKB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
-; RV64ZVKG: .attribute 5, "rv64i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
-; RV64ZVKN: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNHA: .attribute 5, "rv64i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
-; RV64ZVKNHB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNED: .attribute 5, "rv64i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
-; RV64ZVKS: .attribute 5, "rv64i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
-; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
-; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
-; RV64ZICOND: .attribute 5, "rv64i2p0_zicond1p0"
+; RV64M: .attribute 5, "rv64i2p1_m2p0"
+; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
+; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
+; RV64A: .attribute 5, "rv64i2p1_a2p1"
+; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
+; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
+; RV64C: .attribute 5, "rv64i2p1_c2p0"
+; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p1_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p1_zihintntl0p2"
+; RV64ZFHMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0"
+; RV64ZFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfh1p0"
+; RV64ZBA: .attribute 5, "rv64i2p1_zba1p0"
+; RV64ZBB: .attribute 5, "rv64i2p1_zbb1p0"
+; RV64ZBC: .attribute 5, "rv64i2p1_zbc1p0"
+; RV64ZBS: .attribute 5, "rv64i2p1_zbs1p0"
+; RV64V: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64H: .attribute 5, "rv64i2p1_h1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZBKB: .attribute 5, "rv64i2p1_zbkb1p0"
+; RV64ZBKC: .attribute 5, "rv64i2p1_zbkc1p0"
+; RV64ZBKX: .attribute 5, "rv64i2p1_zbkx1p0"
+; RV64ZKND: .attribute 5, "rv64i2p1_zknd1p0"
+; RV64ZKNE: .attribute 5, "rv64i2p1_zkne1p0"
+; RV64ZKNH: .attribute 5, "rv64i2p1_zknh1p0"
+; RV64ZKSED: .attribute 5, "rv64i2p1_zksed1p0"
+; RV64ZKSH: .attribute 5, "rv64i2p1_zksh1p0"
+; RV64ZKR: .attribute 5, "rv64i2p1_zkr1p0"
+; RV64ZKN: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV64ZKS: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV64ZKT: .attribute 5, "rv64i2p1_zkt1p0"
+; RV64ZK: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV64COMBINEINTOZK: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV64ZICBOM: .attribute 5, "rv64i2p1_zicbom1p0"
+; RV64ZICBOZ: .attribute 5, "rv64i2p1_zicboz1p0"
+; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
+; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
+; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
+; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
+; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
+; RV64XTHEADBA: .attribute 5, "rv64i2p1_xtheadba1p0"
+; RV64XTHEADBB: .attribute 5, "rv64i2p1_xtheadbb1p0"
+; RV64XTHEADBS: .attribute 5, "rv64i2p1_xtheadbs1p0"
+; RV64XTHEADCMO: .attribute 5, "rv64i2p1_xtheadcmo1p0"
+; RV64XTHEADCONDMOV: .attribute 5, "rv64i2p1_xtheadcondmov1p0"
+; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
+; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0"
+; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0"
+; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0"
+; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
+; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
+; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1"
+; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0"
+; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0"
+; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0"
+; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
+; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
+; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p1"
+; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index b91baa20bdc7f..64a4d92f31451 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -5,13 +5,10 @@
# RUN: | FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
.attribute arch, "rv32i"
-# CHECK: attribute 5, "rv32i2p0"
+# CHECK: attribute 5, "rv32i2p1"
-.attribute arch, "rv32i2"
-# CHECK: attribute 5, "rv32i2p0"
-
-.attribute arch, "rv32i2p0"
-# CHECK: attribute 5, "rv32i2p0"
+.attribute arch, "rv32i2p1"
+# CHECK: attribute 5, "rv32i2p1"
.attribute arch, "rv32e"
# CHECK: attribute 5, "rv32e2p0"
@@ -19,223 +16,223 @@
.attribute arch, "rv64e"
# CHECK-RV64: attribute 5, "rv64e2p0"
-.attribute arch, "rv32i2_m2"
-# CHECK: attribute 5, "rv32i2p0_m2p0"
+.attribute arch, "rv32i2p1_m2"
+# CHECK: attribute 5, "rv32i2p1_m2p0"
-.attribute arch, "rv32i2_ma"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0"
+.attribute arch, "rv32i2p1_ma"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1"
.attribute arch, "rv32g"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0"
.attribute arch, "rv32imafdc"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
-.attribute arch, "rv32i2p0_mafdc"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv32i2p1_mafdc"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
-.attribute arch, "rv32ima2p0_fdc"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv32ima2p1_fdc"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
-.attribute arch, "rv32ima2p0_fdc"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv32ima2p1_fdc"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
.attribute arch, "rv32iv"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl32b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl64b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl128b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl256b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl512b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl1024b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl2048b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl4096b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
.attribute arch, "rv32ivzvl8192b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
.attribute arch, "rv32ivzvl16384b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
.attribute arch, "rv32ivzvl32768b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
.attribute arch, "rv32ivzvl65536b"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"
.attribute arch, "rv32izve32x"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32ifzve32f"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32izve64x"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ifzve64f"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32ifdzve64d"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32izicbom"
-# CHECK: attribute 5, "rv32i2p0_zicbom1p0"
+# CHECK: attribute 5, "rv32i2p1_zicbom1p0"
.attribute arch, "rv32izicboz"
-# CHECK: attribute 5, "rv32i2p0_zicboz1p0"
+# CHECK: attribute 5, "rv32i2p1_zicboz1p0"
.attribute arch, "rv32izicbop"
-# CHECK: attribute 5, "rv32i2p0_zicbop1p0"
+# CHECK: attribute 5, "rv32i2p1_zicbop1p0"
## Experimental extensions require version string to be explicitly specified
.attribute arch, "rv32izba1p0"
-# CHECK: attribute 5, "rv32i2p0_zba1p0"
+# CHECK: attribute 5, "rv32i2p1_zba1p0"
.attribute arch, "rv32izbb1p0"
-# CHECK: attribute 5, "rv32i2p0_zbb1p0"
+# CHECK: attribute 5, "rv32i2p1_zbb1p0"
.attribute arch, "rv32izbc1p0"
-# CHECK: attribute 5, "rv32i2p0_zbc1p0"
+# CHECK: attribute 5, "rv32i2p1_zbc1p0"
.attribute arch, "rv32i_zve64x_zvkb0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvkg0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
.attribute arch, "rv32i_zve64x_zvkn0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvknha0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
.attribute arch, "rv32i_zve64x_zvknhb0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
.attribute arch, "rv32i_zve32x_zvkned0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
.attribute arch, "rv32i_zve32x_zvks0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
.attribute arch, "rv32i_zve32x_zvksed0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
.attribute arch, "rv32i_zve32x_zvksh0p3"
-# CHECK: attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
.attribute arch, "rv32izbs1p0"
-# CHECK: attribute 5, "rv32i2p0_zbs1p0"
+# CHECK: attribute 5, "rv32i2p1_zbs1p0"
.attribute arch, "rv32ifzfhmin1p0"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
.attribute arch, "rv32ifzfh1p0"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfh1p0"
.attribute arch, "rv32izfinx"
-# CHECK: attribute 5, "rv32i2p0_zfinx1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zfinx1p0"
.attribute arch, "rv32izfinx_zdinx"
-# CHECK: attribute 5, "rv32i2p0_zfinx1p0_zdinx1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0"
.attribute arch, "rv32izfinx_zhinxmin"
-# CHECK: attribute 5, "rv32i2p0_zfinx1p0_zhinxmin1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0"
.attribute arch, "rv32izfinx_zhinx1p0"
-# CHECK: attribute 5, "rv32i2p0_zfinx1p0_zhinx1p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0"
.attribute arch, "rv32i_zbkb1p0"
-# CHECK: attribute 5, "rv32i2p0_zbkb1p0"
+# CHECK: attribute 5, "rv32i2p1_zbkb1p0"
.attribute arch, "rv32i_zbkc1p0"
-# CHECK: attribute 5, "rv32i2p0_zbkc1p0"
+# CHECK: attribute 5, "rv32i2p1_zbkc1p0"
.attribute arch, "rv32i_zbkx1p0"
-# CHECK: attribute 5, "rv32i2p0_zbkx1p0"
+# CHECK: attribute 5, "rv32i2p1_zbkx1p0"
.attribute arch, "rv32i_zknd1p0"
-# CHECK: attribute 5, "rv32i2p0_zknd1p0"
+# CHECK: attribute 5, "rv32i2p1_zknd1p0"
.attribute arch, "rv32i_zkne1p0"
-# CHECK: attribute 5, "rv32i2p0_zkne1p0"
+# CHECK: attribute 5, "rv32i2p1_zkne1p0"
.attribute arch, "rv32i_zknh1p0"
-# CHECK: attribute 5, "rv32i2p0_zknh1p0"
+# CHECK: attribute 5, "rv32i2p1_zknh1p0"
.attribute arch, "rv32i_zksed1p0"
-# CHECK: attribute 5, "rv32i2p0_zksed1p0"
+# CHECK: attribute 5, "rv32i2p1_zksed1p0"
.attribute arch, "rv32i_zksh1p0"
-# CHECK: attribute 5, "rv32i2p0_zksh1p0"
+# CHECK: attribute 5, "rv32i2p1_zksh1p0"
.attribute arch, "rv32i_zkr1p0"
-# CHECK: attribute 5, "rv32i2p0_zkr1p0"
+# CHECK: attribute 5, "rv32i2p1_zkr1p0"
.attribute arch, "rv32i_zkn1p0"
-# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+# CHECK: attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
.attribute arch, "rv32i_zks1p0"
-# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+# CHECK: attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
.attribute arch, "rv32i_zkt1p0"
-# CHECK: attribute 5, "rv32i2p0_zkt1p0"
+# CHECK: attribute 5, "rv32i2p1_zkt1p0"
.attribute arch, "rv32i_zk1p0"
-# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+# CHECK: attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
.attribute arch, "rv32izihintntl0p2"
-# CHECK: attribute 5, "rv32i2p0_zihintntl0p2"
+# CHECK: attribute 5, "rv32i2p1_zihintntl0p2"
.attribute arch, "rv32iczihintntl0p2"
-# CHECK: attribute 5, "rv32i2p0_c2p0_zihintntl0p2"
+# CHECK: attribute 5, "rv32i2p1_c2p0_zihintntl0p2"
.attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
.attribute arch, "rv32izca1p0"
-# CHECK: attribute 5, "rv32i2p0_zca1p0"
+# CHECK: attribute 5, "rv32i2p1_zca1p0"
.attribute arch, "rv32izcd1p0"
-# CHECK: attribute 5, "rv32i2p0_zcd1p0"
+# CHECK: attribute 5, "rv32i2p1_zcd1p0"
.attribute arch, "rv32izcf1p0"
-# CHECK: attribute 5, "rv32i2p0_zcf1p0"
+# CHECK: attribute 5, "rv32i2p1_zcf1p0"
.attribute arch, "rv32izcb1p0"
-# CHECK: attribute 5, "rv32i2p0_zca1p0_zcb1p0"
+# CHECK: attribute 5, "rv32i2p1_zca1p0_zcb1p0"
.attribute arch, "rv32izawrs1p0"
-# CHECK: attribute 5, "rv32i2p0_zawrs1p0"
+# CHECK: attribute 5, "rv32i2p1_zawrs1p0"
.attribute arch, "rv32iztso0p1"
-# CHECK: attribute 5, "rv32i2p0_ztso0p1"
+# CHECK: attribute 5, "rv32i2p1_ztso0p1"
.attribute arch, "rv32izicsr2p0"
-# CHECK: attribute 5, "rv32i2p0_zicsr2p0"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0"
.attribute arch, "rv32izifencei2p0"
-# CHECK: attribute 5, "rv32i2p0_zifencei2p0"
+# CHECK: attribute 5, "rv32i2p1_zifencei2p0"
.attribute arch, "rv32izfa0p1"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zfa0p1"
+# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1"
.attribute arch, "rv32izicond1p0"
-# CHECK: attribute 5, "rv32i2p0_zicond1p0"
+# CHECK: attribute 5, "rv32i2p1_zicond1p0"
diff --git a/llvm/test/MC/RISCV/attribute-with-insts.s b/llvm/test/MC/RISCV/attribute-with-insts.s
index df180b70dd1ec..c122e349403dc 100644
--- a/llvm/test/MC/RISCV/attribute-with-insts.s
+++ b/llvm/test/MC/RISCV/attribute-with-insts.s
@@ -10,7 +10,7 @@
# RUN: | llvm-objdump --triple=riscv64 -d -M no-aliases - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
# CHECK-INST: lr.w t0, (t1)
lr.w t0, (t1)
diff --git a/llvm/test/MC/RISCV/attribute-with-option.s b/llvm/test/MC/RISCV/attribute-with-option.s
index 749717cb7a550..a352489b078b8 100644
--- a/llvm/test/MC/RISCV/attribute-with-option.s
+++ b/llvm/test/MC/RISCV/attribute-with-option.s
@@ -9,7 +9,7 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+e -filetype=obj -o - \
# RUN: | llvm-readobj -A - | FileCheck %s
-.attribute arch, "rv32i2p0"
+.attribute arch, "rv32i2p1"
## Invalid operand for RV32E, because x16 is an invalid register for RV32E.
## Use RV32I to assemble, since it will not trigger an assembly error.
lui x16, 1
@@ -18,4 +18,4 @@ lui x16, 1
## option.
# CHECK: Tag: 5
# CHECK-NEXT: TagName: arch
-# CHECK-NEXT: Value: rv32i2p0
+# CHECK-NEXT: Value: rv32i2p1
diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s
index b7ad98bb6fe23..d36fdd18bdd9c 100644
--- a/llvm/test/MC/RISCV/attribute.s
+++ b/llvm/test/MC/RISCV/attribute.s
@@ -6,8 +6,8 @@
.attribute stack_align, 16
# CHECK: attribute 4, 16
-.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0"
-# CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_c2p0"
+.attribute arch, "rv32i2p1_m2p0_a2p1_c2p0"
+# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_c2p0"
.attribute unaligned_access, 0
# CHECK: attribute 6, 0
diff --git a/llvm/test/MC/RISCV/invalid-attribute.s b/llvm/test/MC/RISCV/invalid-attribute.s
index 3514452997266..3e1fc3b81221b 100644
--- a/llvm/test/MC/RISCV/invalid-attribute.s
+++ b/llvm/test/MC/RISCV/invalid-attribute.s
@@ -9,8 +9,8 @@
.attribute arch, "foo"
# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,e,g}
-.attribute arch, "rv32i2p0_y2p0"
-# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y'
+.attribute arch, "rv32i2p1_y2p0"
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_y2p0', invalid standard user-level extension 'y'
.attribute stack_align, "16"
# CHECK: [[@LINE-1]]:25: error: expected numeric constant
diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s b/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
index 5ae7bfcb0290e..078c3f760c7ea 100644
--- a/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
+++ b/llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
@@ -17,10 +17,10 @@
# CHECK-OBJ-NEXT: TagName: stack_align
# CHECK-OBJ-NEXT: Description: Stack alignment is 16-bytes
-.attribute Tag_arch, "rv32i2p0_m2p0_a2p0_c2p0"
+.attribute Tag_arch, "rv32i2p1_m2p0_a2p1_c2p0"
# CHECK-OBJ: Tag: 5
# CHECK-OBJ-NEXT: TagName: arch
-# CHECK-OBJ-NEXT: Value: rv32i2p0_m2p0_a2p0_c2p0
+# CHECK-OBJ-NEXT: Value: rv32i2p1_m2p0_a2p1_c2p0
.attribute Tag_unaligned_access, 0
# CHECK-OBJ: Tag: 6
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index d9d3e45c1668a..8a353360f9f27 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -130,7 +130,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV32I = **MaybeRV32I;
RISCVISAInfo::OrderedExtensionMap ExtsRV32I = InfoRV32I.getExtensions();
EXPECT_EQ(ExtsRV32I.size(), 1UL);
- EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVExtensionInfo{2, 1}));
EXPECT_EQ(InfoRV32I.getXLen(), 32U);
EXPECT_EQ(InfoRV32I.getFLen(), 0U);
@@ -147,12 +147,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
ASSERT_THAT_EXPECTED(MaybeRV32G, Succeeded());
RISCVISAInfo &InfoRV32G = **MaybeRV32G;
RISCVISAInfo::OrderedExtensionMap ExtsRV32G = InfoRV32G.getExtensions();
- EXPECT_EQ(ExtsRV32G.size(), 5UL);
- EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_EQ(ExtsRV32G.size(), 7UL);
+ EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVExtensionInfo{2, 1}));
EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVExtensionInfo{2, 0}));
- EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVExtensionInfo{2, 0}));
- EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVExtensionInfo{2, 0}));
- EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVExtensionInfo{2, 1}));
+ EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVExtensionInfo{2, 2}));
+ EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVExtensionInfo{2, 2}));
+ EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(ExtsRV32G.at("zifencei") == (RISCVExtensionInfo{2, 0}));
EXPECT_EQ(InfoRV32G.getXLen(), 32U);
EXPECT_EQ(InfoRV32G.getFLen(), 64U);
@@ -161,7 +163,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
RISCVISAInfo &InfoRV64I = **MaybeRV64I;
RISCVISAInfo::OrderedExtensionMap ExtsRV64I = InfoRV64I.getExtensions();
EXPECT_EQ(ExtsRV64I.size(), 1UL);
- EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVExtensionInfo{2, 1}));
EXPECT_EQ(InfoRV64I.getXLen(), 64U);
EXPECT_EQ(InfoRV64I.getFLen(), 0U);
@@ -178,12 +180,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
ASSERT_THAT_EXPECTED(MaybeRV64G, Succeeded());
RISCVISAInfo &InfoRV64G = **MaybeRV64G;
RISCVISAInfo::OrderedExtensionMap ExtsRV64G = InfoRV64G.getExtensions();
- EXPECT_EQ(ExtsRV64G.size(), 5UL);
- EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_EQ(ExtsRV64G.size(), 7UL);
+ EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVExtensionInfo{2, 1}));
EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVExtensionInfo{2, 0}));
- EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVExtensionInfo{2, 0}));
- EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVExtensionInfo{2, 0}));
- EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVExtensionInfo{2, 1}));
+ EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVExtensionInfo{2, 2}));
+ EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVExtensionInfo{2, 2}));
+ EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(ExtsRV64G.at("zifencei") == (RISCVExtensionInfo{2, 0}));
EXPECT_EQ(InfoRV64G.getXLen(), 64U);
EXPECT_EQ(InfoRV64G.getFLen(), 64U);
}
@@ -237,7 +241,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
RISCVISAInfo &Info = **MaybeISAInfo;
RISCVISAInfo::OrderedExtensionMap Exts = Info.getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1}));
}
// Checks that supported extensions aren't incorrectly ignored when a
@@ -250,11 +254,11 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
}
TEST(ParseArchString, AcceptsVersionInLongOrShortForm) {
- for (StringRef Input : {"rv64i2", "rv64i2p0"}) {
+ for (StringRef Input : {"rv64i2p1"}) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
- EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1}));
}
for (StringRef Input : {"rv32i_zfinx1", "rv32i_zfinx1p0"}) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
@@ -265,6 +269,9 @@ TEST(ParseArchString, AcceptsVersionInLongOrShortForm) {
}
TEST(ParseArchString, RejectsUnrecognizedExtensionVersionsByDefault) {
+ EXPECT_EQ(
+ toString(RISCVISAInfo::parseArchString("rv64i2p", true).takeError()),
+ "minor version number missing after 'p' for extension 'i'");
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv64i1p0", true).takeError()),
"unsupported version number 1.0 for extension 'i'");
@@ -286,7 +293,7 @@ TEST(ParseArchString,
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1}));
}
for (StringRef Input : {"rv32e0p1", "rv32e99p99", "rv64e0p1", "rv64e99p99"}) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true);
@@ -304,7 +311,7 @@ TEST(ParseArchString,
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
EXPECT_EQ(Exts.size(), 1UL);
- EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 0}));
+ EXPECT_TRUE(Exts.at("i") == (RISCVExtensionInfo{2, 1}));
}
}
@@ -313,13 +320,14 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
- EXPECT_EQ(Exts.size(), 7UL);
+ EXPECT_EQ(Exts.size(), 8UL);
EXPECT_EQ(Exts.count("i"), 1U);
EXPECT_EQ(Exts.count("m"), 1U);
EXPECT_EQ(Exts.count("a"), 1U);
EXPECT_EQ(Exts.count("f"), 1U);
EXPECT_EQ(Exts.count("d"), 1U);
EXPECT_EQ(Exts.count("c"), 1U);
+ EXPECT_EQ(Exts.count("zicsr"), 1U);
EXPECT_EQ(Exts.count("zifencei"), 1U);
}
}
@@ -417,10 +425,11 @@ TEST(ParseArchString, AddsImpliedExtensions) {
ASSERT_THAT_EXPECTED(MaybeRV64ID, Succeeded());
RISCVISAInfo::OrderedExtensionMap ExtsRV64ID =
(*MaybeRV64ID)->getExtensions();
- EXPECT_EQ(ExtsRV64ID.size(), 3UL);
+ EXPECT_EQ(ExtsRV64ID.size(), 4UL);
EXPECT_EQ(ExtsRV64ID.count("i"), 1U);
EXPECT_EQ(ExtsRV64ID.count("f"), 1U);
EXPECT_EQ(ExtsRV64ID.count("d"), 1U);
+ EXPECT_EQ(ExtsRV64ID.count("zicsr"), 1U);
auto MaybeRV32IZKN = RISCVISAInfo::parseArchString("rv64izkn", true);
ASSERT_THAT_EXPECTED(MaybeRV32IZKN, Succeeded());
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