[PATCH] D147154: [AMDGPU][GlobalISel] Add codegen support for S_INDIRECT_REG_WRITE_MOVREL_B32_V[9|10|11|12]

Thu Mar 30 08:37:46 PDT 2023

foad accepted this revision.
foad added inline comments.
This revision is now accepted and ready to land.

================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir:178
+---
+name: insert_vector_elt_s_s32_v9s32
+legalized: true
----------------
matejam wrote:
> foad wrote:
> > matejam wrote:
> > > foad wrote:
> > > > How would these tests fail without your patch?
> > > The compiler wouldn't select S_INDIRECT_REG_WRITE_MOVREL_B32_V9, but would select S_INDIRECT_REG_WRITE_MOVREL_B32_V16 instead.
> > Then maybe precommit the tests (no review required) and rebase?
> The reason of the MIR test failure is because of the machine verifier, without it the test passes.
> "Expected a SReg_512 register, but got a SGPR_288/SGPR_320/SGPR_352/SGPR_388 register."
Ack.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147154/new/

https://reviews.llvm.org/D147154