[PATCH] D147096: AMDGPU: Created a sub-register class for the return address operand in the tail call return instruction

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D147096#4229413 <https://reviews.llvm.org/D147096#4229413>, @cfang wrote:

> In D147096#4229261 <https://reviews.llvm.org/D147096#4229261>, @cdevadas wrote:
>
>> What will happen to `getMinimalPhysRegClass` query for SGPR_64 registers?
>> If this returns the new register class, ccr_sgpr_64, that's not the desired behavior.
>
> getMinimalPhysRegClass should always return the minimal physical register class. I think CCR_SGPR_64
> has all the properties of SGPR_64, so we won't have any issue for the (srcReg, RC) pair.

But we want the most lax register class possible. CCR_SGPR_64 should be used in this context and this context alone


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147096/new/

https://reviews.llvm.org/D147096