[PATCH] D147119: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 509388.
craig.topper added a comment.

Fix polarity of IsUnitStrided flags.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147119/new/

https://reviews.llvm.org/D147119

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

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