[PATCH] D147119: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1218
+                               /*IsStore*/ false,
+                               /*IsUnitStrided*/ false);
+  case Intrinsic::riscv_vse:
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I am confused by the argument name? vle and vleff is `Unit-Stride Instructions` but `IsUnitStrided` is false?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147119/new/

https://reviews.llvm.org/D147119