[llvm] f38aba1 - [X86] MatchVectorAllZeroTest - return X86::CondCode instead of constant node. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-03-28T15:19:17+01:00
New Revision: f38aba1866ef68da64921eb0270e93880f5f704b

URL: https://github.com/llvm/llvm-project/commit/f38aba1866ef68da64921eb0270e93880f5f704b
DIFF: https://github.com/llvm/llvm-project/commit/f38aba1866ef68da64921eb0270e93880f5f704b.diff

LOG: [X86] MatchVectorAllZeroTest - return X86::CondCode instead of constant node. NFC.

Just return the X86::CondCode enum value instead of creating the target constant node in multiple locations, letting us use the getSETCC helper.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ecb5036313a6..b2b816f04239 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24419,7 +24419,7 @@ static SDValue LowerVectorAllZero(const SDLoc &DL, SDValue V, ISD::CondCode CC,
 static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
                                       const SDLoc &DL,
                                       const X86Subtarget &Subtarget,
-                                      SelectionDAG &DAG, SDValue &X86CC) {
+                                      SelectionDAG &DAG, X86::CondCode &X86CC) {
   assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Unsupported ISD::CondCode");
 
   if (!Subtarget.hasSSE2() || !Op->hasOneUse())
@@ -24467,24 +24467,18 @@ static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
       VecIns.push_back(DAG.getNode(ISD::OR, DL, VT, LHS, RHS));
     }
 
-    X86::CondCode CCode;
     if (SDValue V = LowerVectorAllZero(DL, VecIns.back(), CC, Mask, Subtarget,
-                                       DAG, CCode)) {
-      X86CC = DAG.getTargetConstant(CCode, DL, MVT::i8);
+                                       DAG, X86CC))
       return V;
-    }
   }
 
   if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
     ISD::NodeType BinOp;
     if (SDValue Match =
             DAG.matchBinOpReduction(Op.getNode(), BinOp, {ISD::OR})) {
-      X86::CondCode CCode;
       if (SDValue V =
-              LowerVectorAllZero(DL, Match, CC, Mask, Subtarget, DAG, CCode)) {
-        X86CC = DAG.getTargetConstant(CCode, DL, MVT::i8);
+              LowerVectorAllZero(DL, Match, CC, Mask, Subtarget, DAG, X86CC))
         return V;
-      }
     }
   }
 
@@ -25684,9 +25678,11 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
     // Try to use PTEST/PMOVMSKB for a tree ORs equality compared with 0.
     // TODO: We could do AND tree with all 1s as well by using the C flag.
     if (isNullConstant(Op1))
-      if (SDValue CmpZ =
-              MatchVectorAllZeroTest(Op0, CC, dl, Subtarget, DAG, X86CC))
+      if (SDValue CmpZ = MatchVectorAllZeroTest(Op0, CC, dl, Subtarget, DAG,
+                                                X86CondCode)) {
+        X86CC = DAG.getTargetConstant(X86CondCode, dl, MVT::i8);
         return CmpZ;
+      }
 
     // Try to lower using KORTEST or KTEST.
     if (SDValue Test = EmitAVX512Test(Op0, Op1, CC, dl, DAG, Subtarget, X86CC))
@@ -54180,11 +54176,10 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
       return V;
 
     if (VT == MVT::i1 && isNullConstant(RHS)) {
-      SDValue X86CC;
+      X86::CondCode X86CC;
       if (SDValue V =
               MatchVectorAllZeroTest(LHS, CC, DL, Subtarget, DAG, X86CC))
-        return DAG.getNode(ISD::TRUNCATE, DL, VT,
-                           DAG.getNode(X86ISD::SETCC, DL, MVT::i8, X86CC, V));
+        return DAG.getNode(ISD::TRUNCATE, DL, VT, getSETCC(X86CC, V, DL, DAG));
     }
 
     if (OpVT.isScalarInteger()) {