[llvm] 3d1068f - [X86] emitFlagsForSetcc - pull out repeated isEquality condcode checks. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 28 07:02:51 PDT 2023
Author: Simon Pilgrim
Date: 2023-03-28T15:02:32+01:00
New Revision: 3d1068ffe17276ac5bc9602f5b413814a474bd63
URL: https://github.com/llvm/llvm-project/commit/3d1068ffe17276ac5bc9602f5b413814a474bd63
DIFF: https://github.com/llvm/llvm-project/commit/3d1068ffe17276ac5bc9602f5b413814a474bd63.diff
LOG: [X86] emitFlagsForSetcc - pull out repeated isEquality condcode checks. NFC.
Most of the combines are for ISD::SETEQ/ISD::SETNE comparisons so do a single early-check for the condcode.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 13e072a577a75..ecb5036313a69 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25611,9 +25611,7 @@ static SDValue EmitAVX512Test(SDValue Op0, SDValue Op1, ISD::CondCode CC,
const SDLoc &dl, SelectionDAG &DAG,
const X86Subtarget &Subtarget,
SDValue &X86CC) {
- // Only support equality comparisons.
- if (CC != ISD::SETEQ && CC != ISD::SETNE)
- return SDValue();
+ assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Unsupported ISD::CondCode");
// Must be a bitcast from vXi1.
if (Op0.getOpcode() != ISD::BITCAST)
@@ -25668,63 +25666,65 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
ISD::CondCode CC, const SDLoc &dl,
SelectionDAG &DAG,
SDValue &X86CC) const {
- // Optimize to BT if possible.
- // Lower (X & (1 << N)) == 0 to BT(X, N).
- // Lower ((X >>u N) & 1) != 0 to BT(X, N).
- // Lower ((X >>s N) & 1) != 0 to BT(X, N).
- if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && isNullConstant(Op1) &&
- (CC == ISD::SETEQ || CC == ISD::SETNE)) {
+ // Equality Combines.
+ if (CC == ISD::SETEQ || CC == ISD::SETNE) {
X86::CondCode X86CondCode;
- if (SDValue BT = LowerAndToBT(Op0, CC, dl, DAG, X86CondCode)) {
- X86CC = DAG.getTargetConstant(X86CondCode, dl, MVT::i8);
- return BT;
- }
- }
-
- // Try to use PTEST/PMOVMSKB for a tree ORs equality compared with 0.
- // TODO: We could do AND tree with all 1s as well by using the C flag.
- if (isNullConstant(Op1) && (CC == ISD::SETEQ || CC == ISD::SETNE))
- if (SDValue CmpZ =
- MatchVectorAllZeroTest(Op0, CC, dl, Subtarget, DAG, X86CC))
- return CmpZ;
- // Try to lower using KORTEST or KTEST.
- if (SDValue Test = EmitAVX512Test(Op0, Op1, CC, dl, DAG, Subtarget, X86CC))
- return Test;
-
- // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
- // these.
- if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
- (CC == ISD::SETEQ || CC == ISD::SETNE)) {
- // If the input is a setcc, then reuse the input setcc or use a new one with
- // the inverted condition.
- if (Op0.getOpcode() == X86ISD::SETCC) {
- bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
+ // Optimize to BT if possible.
+ // Lower (X & (1 << N)) == 0 to BT(X, N).
+ // Lower ((X >>u N) & 1) != 0 to BT(X, N).
+ // Lower ((X >>s N) & 1) != 0 to BT(X, N).
+ if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && isNullConstant(Op1)) {
+ if (SDValue BT = LowerAndToBT(Op0, CC, dl, DAG, X86CondCode)) {
+ X86CC = DAG.getTargetConstant(X86CondCode, dl, MVT::i8);
+ return BT;
+ }
+ }
+
+ // Try to use PTEST/PMOVMSKB for a tree ORs equality compared with 0.
+ // TODO: We could do AND tree with all 1s as well by using the C flag.
+ if (isNullConstant(Op1))
+ if (SDValue CmpZ =
+ MatchVectorAllZeroTest(Op0, CC, dl, Subtarget, DAG, X86CC))
+ return CmpZ;
+
+ // Try to lower using KORTEST or KTEST.
+ if (SDValue Test = EmitAVX512Test(Op0, Op1, CC, dl, DAG, Subtarget, X86CC))
+ return Test;
+
+ // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms
+ // of these.
+ if (isOneConstant(Op1) || isNullConstant(Op1)) {
+ // If the input is a setcc, then reuse the input setcc or use a new one
+ // with the inverted condition.
+ if (Op0.getOpcode() == X86ISD::SETCC) {
+ bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
+
+ X86CC = Op0.getOperand(0);
+ if (Invert) {
+ X86CondCode = (X86::CondCode)Op0.getConstantOperandVal(0);
+ X86CondCode = X86::GetOppositeBranchCondition(X86CondCode);
+ X86CC = DAG.getTargetConstant(X86CondCode, dl, MVT::i8);
+ }
- X86CC = Op0.getOperand(0);
- if (Invert) {
- X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
- CCode = X86::GetOppositeBranchCondition(CCode);
- X86CC = DAG.getTargetConstant(CCode, dl, MVT::i8);
+ return Op0.getOperand(1);
}
-
- return Op0.getOperand(1);
}
- }
- // Try to use the carry flag from the add in place of an separate CMP for:
- // (seteq (add X, -1), -1). Similar for setne.
- if (isAllOnesConstant(Op1) && Op0.getOpcode() == ISD::ADD &&
- Op0.getOperand(1) == Op1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
- if (isProfitableToUseFlagOp(Op0)) {
- SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
+ // Try to use the carry flag from the add in place of an separate CMP for:
+ // (seteq (add X, -1), -1). Similar for setne.
+ if (isAllOnesConstant(Op1) && Op0.getOpcode() == ISD::ADD &&
+ Op0.getOperand(1) == Op1) {
+ if (isProfitableToUseFlagOp(Op0)) {
+ SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
- SDValue New = DAG.getNode(X86ISD::ADD, dl, VTs, Op0.getOperand(0),
- Op0.getOperand(1));
- DAG.ReplaceAllUsesOfValueWith(SDValue(Op0.getNode(), 0), New);
- X86::CondCode CCode = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
- X86CC = DAG.getTargetConstant(CCode, dl, MVT::i8);
- return SDValue(New.getNode(), 1);
+ SDValue New = DAG.getNode(X86ISD::ADD, dl, VTs, Op0.getOperand(0),
+ Op0.getOperand(1));
+ DAG.ReplaceAllUsesOfValueWith(SDValue(Op0.getNode(), 0), New);
+ X86CondCode = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
+ X86CC = DAG.getTargetConstant(X86CondCode, dl, MVT::i8);
+ return SDValue(New.getNode(), 1);
+ }
}
}
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