[PATCH] D145315: AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnable

[Carl Ritson via Phabricator via llvm-commits]

critson added a comment.

LGTM, but one question about the diff preparation.



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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:282
+  unsigned PSInputEnable = 0;
+
   SIMode Mode;
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I don't understand this part of the diff, since this is how the header is already defined.


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  https://reviews.llvm.org/D145315/new/

https://reviews.llvm.org/D145315