[llvm] 5c5fe3a - [RISCV] Relax opcode restriction for .insn.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-27T10:24:55-07:00
New Revision: 5c5fe3afff12b41d34477977c07c71337fa4ba9d

URL: https://github.com/llvm/llvm-project/commit/5c5fe3afff12b41d34477977c07c71337fa4ba9d
DIFF: https://github.com/llvm/llvm-project/commit/5c5fe3afff12b41d34477977c07c71337fa4ba9d.diff

LOG: [RISCV] Relax opcode restriction for .insn.

I recently added a check to make sure the lower 2 bits of the opcode
were 0x3. A post commit comment pointed out this would be allowed
for a custom extension when C is not supported.

Note, binutils does have this restriction.

Added: 
    

Modified: 
    llvm/test/MC/RISCV/insn-invalid.s

Removed: 
    


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diff  --git a/llvm/test/MC/RISCV/insn-invalid.s b/llvm/test/MC/RISCV/insn-invalid.s
index 82fdd7b579ea..e9fdc4042c1d 100644
--- a/llvm/test/MC/RISCV/insn-invalid.s
+++ b/llvm/test/MC/RISCV/insn-invalid.s
@@ -14,12 +14,12 @@
 .insn q  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format
 
 # Invalid immediate
-.insn i  0x99,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127]
+.insn i  0x99,  0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be a valid opcode name or an immediate in the range [0, 127]
 .insn r  0x33,  8,  0, a0, a1, a2 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7]
 .insn r4 0x43,  0,  4, fa0, fa1, fa2, fa3 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]
 
 # Unrecognized opcode name
-.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3
+.insn r UNKNOWN, 0, a1, a2, a3 #CHECK: :[[@LINE]]:9: error: opcode must be a valid opcode name or an immediate in the range [0, 127]
 
 # Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed.
 .insn_i  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive